637xx_regs.inc

HID规范和一个基于CYPRESS FX2 的例子

; processor registers
Port0:				equ	00h
Port1:				equ	01h
Port2:				equ	02h

Port0_Interrupt:		equ	04h
Port1_Interrupt:		equ	05h
Port0_Interrupt_Polarity:	equ	06h
Port1_Interrupt_Polarity:	equ	07h

Port0_Mode0:			equ	0Ah
Port0_Mode1:			equ	0Bh
Port1_Mode0:			equ	0Ch
Port1_Mode1:			equ	0Dh


Usb_Address:			equ	10h

Ep0_Count:			equ	11h
Ep0_Mode:			equ	12h
Ep1_Count:			equ	13h
Ep1_Mode:			equ	14h
Ep2_Count:			equ	15h
Ep2_Mode:			equ	16h

Usb_Status_Control:		equ	1Fh

Global_Interrupt:		equ	20h
Endpoint_Interrupt:		equ	21h

Timer_Lsb:			equ	24h
Timer_Msb:			equ	25h

Watchdog:			equ	26h

Capture_TimerA_Rising:		equ	40h
Capture_TimerA_Falling:		equ	41h
Capture_TimerB_Rising:		equ	42h
Capture_TimerB_Falling:		equ	43h
Capture_Timer_Config:		equ	44h
Capture_Timer_Status:		equ	45h

SPI_Data:			equ	60h
SPI_Control:			equ	61h

Clock_Config:			equ	F8h
Processor_Status_Control: 	equ	FFh

; Port 2 Data Register 0x02 bit assignments
SCLK:				equ	20h
DPLUS:				equ	20h
SDATA:				equ	10h
DMINUS:				equ	10h
XTALIN:				equ	02h
VREG:				equ	01h

; USB Port status and control register 0x1F bit assignments
PS2_PULLUP:			equ	80h
VREG_ENABLE:			equ	40h
USB_PS2_MODE:			equ	20h
BUS_ACTIVITY:			equ	08h
CONTROL0:			equ	01h
CONTROL1:			equ	02h
CONTROL2:			equ	04h

NOT_FORCING:			equ	00h
FORCE_K:			equ	01h
FORCE_J:			equ	02h
FORCE_SE0:			equ	03h
FORCEBOTH_LOW:			equ	40h
FORCESDATA_LOW:			equ	05h
FORCESCLK_LOW:			equ	06h
FORCE_HIZ:			equ	07h

;Port Modes
MODE0_RESISTIVE_MODE:		equ	00h
MODE1_RESISTIVE_MODE:		equ	FFh

; USB Device Address Registers 0x10 bit assignments
ADDRESS_ENABLE:			equ	80h
ADDRESS_MASK:			equ	7Fh

; USB Device EP0 Mode Register 0x12
EP0_SETUP:			equ	80h
EP0_IN:				equ	40h
EP0_OUT:			equ	20h
EP0_ACK:			equ	10h
MODE_MASK:			equ	0Fh

; USB Device Endpoint Mode Registers 0x14, 0x16
EP_STALL:			equ	80h
EP_ACK:				equ	10h

; USB Device Counter Registers 0x11, 0x13, 0x15
DATA_TOGGLE:			equ	80h
DATA_VALID:			equ	40h
BYTE_COUNT:			equ	0Fh

;Processor Status and Control Register 0xFF
IRQ_PENDING:			equ	80h
WDR:				equ	40h
USB_RESET:			equ	20h
POR_RESET:			equ	10h
SUSPEND:			equ	08h
INT_ENABLE_SENSE:		equ	04h
RUN:				equ	01h

; global interrupt enable register 0x20 bit assignments
WAKEUP_INT:			equ	80h
GPIO_INT:			equ	40h
1MS_INT:			equ	04h
128US_INT:			equ	02h
USB_RESET_INT:			equ	01h

; USB Endpoint Interrupt Enable Register 0x21 bit assignments
EP2_INT:			equ	04h
EP1_INT:			equ	02h
EP0_INT:			equ	01h

; Clock Configuration Register 0xF8 bit assignments
EXT_DELAY:			equ	80h
WAKEUP_ADJUST2:			equ	40h
WAKEUP_ADJUST1:			equ	20h
WAKEUP_ADJUST0:			equ	10h
LVR_ENABLE:			equ	08h
PRECISION_CLK_ENABLE:		equ	04h
INTERNAL_CLK:			equ	02h
EXTERNAL_CLK:			equ	01h

; USB register mode encoding
DISABLE:			equ	00h
NAK_IN_OUT:			equ	01h
STATUS_OUT_ONLY:		equ	02h
STALL_IN_OUT:			equ	03h
IGNORE_IN_OUT:			equ	04h
STATUS_IN_ONLY:			equ	06h
ISOCHRONOUS_IN:			equ	07h
NAK_OUT:			equ	08h
ACK_OUT:			equ	09h
NAK_OUT_STATUS_IN:		equ	0Ah
ACK_OUT_NAK_IN:			equ	0Bh
NAK_IN:				equ	0Ch
ACK_IN:				equ	0Dh
NAK_IN_STATUS_OUT:		equ	0Eh
ACK_IN_STATUS_OUT:		equ	0Fh

;RAM locations
TOP_OF_RAM:			equ	FFh
BOTTOM_OF_RAM:			equ	00h

SET:				equ	FFh
CLEAR:				equ	00h