ne2000adapter.h

VC++ 6.0NDIS, NDIS Miniport NIC Drivers

// File: ne2000adapter.h
// Purpose: Header file for the ne2000 adapter (this is where most of the work is done)

#ifndef _NE2000ADAPTER_H_
#define _NE2000ADAPTER_H_




// default values when we cant find entries int the registry

// controls the number of transmit buffers on the packet.
// Choices are 1 through 12.
#define DEFAULT_NUMBUFFERS 12
#define DEFAULT_MULTICASTLISTMAX 8
#define DEFAULT_IOBASEADDR 0x300
#define DEFAULT_INTERRUPTNUMBER 3



#define CIS_NET_ADDR_OFFSET 0xff0

// Create a macro for moving memory from place to place.  Makes
// the code more readable and portable in case we ever support
// a shared memory Ne2000 adapter.
#define NE2000_MOVE_MEM(dest,src,size) NdisMoveMemory(dest,src,size)

// The status of transmit buffers.
typedef enum {
    EMPTY = 0x00,
    FULL = 0x02
} BUFFER_STATUS;


// Type of an interrupt.
typedef enum {
    RECEIVE    = 0x01,
    TRANSMIT   = 0x02,
    OVERFLOW   = 0x04,
    COUNTER    = 0x08,
    UNKNOWN    = 0x10
} INTERRUPT_TYPE;


// Result of IndicatePacket().
typedef enum {
    INDICATE_OK,
    SKIPPED,
    ABORT,
    CARD_BAD
} INDICATE_STATUS;



// Size of the ethernet header
#define NE2000_HEADER_SIZE 14

// Number of bytes allowed in a lookahead (max)
#define NE2000_MAX_LOOKAHEAD (252 - NE2000_HEADER_SIZE)

// Maximum number of transmit buffers on the card.
#define MAX_XMIT_BUFS   12

// Definition of a transmit buffer.
typedef UINT XMIT_BUF;

// Number of 256-byte buffers in a transmit buffer.
#define BUFS_PER_TX 1

// Size of a single transmit buffer.
#define TX_BUF_SIZE (BUFS_PER_TX*256)



// Valid value ranges for the IoBaseAddress.
#define MIN_IOBASEADDR 0x0120
#define MAX_IOBASEADDR 0xc3d0

// Valid value ranges for the InterruptNumber.
#define MIN_IRQ 2
#define MAX_IRQ 15

//  Types of Ne2000 cards.
#define NE2000_ISA                  0
#define NE2000_PCMCIA               1

// Microchannel IRQ POS register mask and shift count
#define MC_IRQ_MASK     0x60
#define MC_IRQ_MASK_UB  0x0E


// Microchannel I/O base address mask and shift count
#define MC_IO_BASE_MASK      0x0E
#define MC_IO_BASE_MASK_UB   0xE0

// Default value for the adapter Info.IoBaseAddr
#define DEFAULT_IOBASEADDR 0x300

#define CIS_NET_ADDR_OFFSET 0xff0


// Offsets from the adapter Info.IoPAddr of the ports used to access
// the 8390 NIC registers.
// 
// The names in parenthesis are the abbreviations by which
// the registers are referred to in the 8390 data sheet.
// 
// Some of the offsets appear more than once
// because they have have relevant page 0 and page 1 values,
// or they are different registers when read than they are
// when written. The notation MSB indicates that only the
// MSB can be set for this register, the LSB is assumed 0.
#define NIC_COMMAND         0x0     // (CR)
#define NIC_PAGE_START      0x1     // (PSTART)   MSB, write-only
#define NIC_PHYS_ADDR       0x1     // (PAR0)     page 1
#define NIC_PAGE_STOP       0x2     // (PSTOP)    MSB, write-only
#define NIC_BOUNDARY        0x3     // (BNRY)     MSB
#define NIC_XMIT_START      0x4     // (TPSR)     MSB, write-only
#define NIC_XMIT_STATUS     0x4     // (TSR)      read-only
#define NIC_XMIT_COUNT_LSB  0x5     // (TBCR0)    write-only
#define NIC_XMIT_COUNT_MSB  0x6     // (TBCR1)    write-only
#define NIC_FIFO            0x6     // (FIFO)     read-only
#define NIC_INTR_STATUS     0x7     // (ISR)
#define NIC_CURRENT         0x7     // (CURR)     page 1
#define NIC_MC_ADDR         0x8     // (MAR0)     page 1
#define NIC_CRDA_LSB        0x8     // (CRDA0)
#define NIC_RMT_ADDR_LSB    0x8     // (RSAR0)
#define NIC_CRDA_MSB        0x9     // (CRDA1)
#define NIC_RMT_ADDR_MSB    0x9     // (RSAR1)
#define NIC_RMT_COUNT_LSB   0xa     // (RBCR0)    write-only
#define NIC_RMT_COUNT_MSB   0xb     // (RBCR1)    write-only
#define NIC_RCV_CONFIG      0xc     // (RCR)      write-only
#define NIC_RCV_STATUS      0xc     // (RSR)      read-only
#define NIC_XMIT_CONFIG     0xd     // (TCR)      write-only
#define NIC_FAE_ERR_CNTR    0xd     // (CNTR0)    read-only
#define NIC_DATA_CONFIG     0xe     // (DCR)      write-only
#define NIC_CRC_ERR_CNTR    0xe     // (CNTR1)    read-only
#define NIC_INTR_MASK       0xf     // (IMR)      write-only
#define NIC_MISSED_CNTR     0xf     // (CNTR2)    read-only
#define NIC_RACK_NIC        0x10    // Byte to read or write
#define NIC_RESET           0x1f    // (RESET)


// 
// Constants for the NIC_COMMAND register.
// 
// Start/stop the card, start transmissions, and select
// which page of registers was seen through the ports.
#define CR_STOP         (UCHAR)0x01        // reset the card
#define CR_START        (UCHAR)0x02        // start the card
#define CR_XMIT         (UCHAR)0x04        // begin transmission
#define CR_NO_DMA       (UCHAR)0x20        // stop remote DMA

#define CR_PS0          (UCHAR)0x40        // low bit of page number
#define CR_PS1          (UCHAR)0x80        // high bit of page number
#define CR_PAGE0        (UCHAR)0x00        // select page 0
#define CR_PAGE1        CR_PS0             // select page 1
#define CR_PAGE2        CR_PS1             // select page 2

#define CR_DMA_WRITE    (UCHAR)0x10        // Write
#define CR_DMA_READ     (UCHAR)0x08        // Read
#define CR_SEND         (UCHAR)0x18        // send


// Constants for the NIC_XMIT_STATUS register.
// 
// Indicate the result of a packet transmission.
#define TSR_XMIT_OK     (UCHAR)0x01        // transmit with no errors
#define TSR_COLLISION   (UCHAR)0x04        // collided at least once
#define TSR_ABORTED     (UCHAR)0x08        // too many collisions
#define TSR_NO_CARRIER  (UCHAR)0x10        // carrier lost
#define TSR_NO_CDH      (UCHAR)0x40        // no collision detect heartbeat


// Constants for the NIC_INTR_STATUS register.
// 
// Indicate the cause of an interrupt.
#define ISR_EMPTY       (UCHAR)0x00        // no bits set in ISR
#define ISR_RCV         (UCHAR)0x01        // packet received with no errors
#define ISR_XMIT        (UCHAR)0x02        // packet transmitted with no errors
#define ISR_RCV_ERR     (UCHAR)0x04        // error on packet reception
#define ISR_XMIT_ERR    (UCHAR)0x08        // error on packet transmission
#define ISR_OVERFLOW    (UCHAR)0x10        // receive buffer overflow
#define ISR_COUNTER     (UCHAR)0x20        // MSB set on tally counter
#define ISR_DMA_DONE    (UCHAR)0x40        // RDC
#define ISR_RESET       (UCHAR)0x80        // (not an interrupt) card is reset


// Constants for the NIC_RCV_CONFIG register.
// 
// Configure what type of packets are received.
#define RCR_REJECT_ERR  (UCHAR)0x00        // reject error packets
#define RCR_BROADCAST   (UCHAR)0x04        // receive broadcast packets
#define RCR_MULTICAST   (UCHAR)0x08        // receive multicast packets
#define RCR_ALL_PHYS    (UCHAR)0x10        // receive ALL directed packets
#define RCR_MONITOR     (UCHAR)0x20        // don't collect packets


// Constants for the NIC_RCV_STATUS register.
// 
// Indicate the status of a received packet.
// 
// These are also used to interpret the status byte in the
// packet header of a received packet.
#define RSR_PACKET_OK   (UCHAR)0x01        // packet received with no errors
#define RSR_CRC_ERROR   (UCHAR)0x02        // packet received with CRC error
#define RSR_MULTICAST   (UCHAR)0x20        // packet received was multicast
#define RSR_DISABLED    (UCHAR)0x40        // received is disabled
#define RSR_DEFERRING   (UCHAR)0x80        // receiver is deferring


// 
// Constants for the NIC_XMIT_CONFIG register.
// 
// Configures how packets are transmitted.
#define TCR_NO_LOOPBACK (UCHAR)0x00        // normal operation
#define TCR_LOOPBACK    (UCHAR)0x02        // loopback (set when NIC is stopped)

#define TCR_INHIBIT_CRC (UCHAR)0x01        // inhibit appending of CRC

#define TCR_NIC_LBK     (UCHAR)0x02        // loopback through the NIC
#define TCR_SNI_LBK     (UCHAR)0x04        // loopback through the SNI
#define TCR_COAX_LBK    (UCHAR)0x06        // loopback to the coax


// Constants for the NIC_DATA_CONFIG register.
// 
// Set data transfer sizes.
#define DCR_BYTE_WIDE   (UCHAR)0x00        // byte-wide DMA transfers
#define DCR_WORD_WIDE   (UCHAR)0x01        // word-wide DMA transfers

#define DCR_LOOPBACK    (UCHAR)0x00        // loopback mode (TCR must be set)
#define DCR_NORMAL      (UCHAR)0x08        // normal operation

#define DCR_FIFO_2_BYTE (UCHAR)0x00        // 2-byte FIFO threshhold
#define DCR_FIFO_4_BYTE (UCHAR)0x20        // 4-byte FIFO threshhold
#define DCR_FIFO_8_BYTE (UCHAR)0x40        // 8-byte FIFO threshhold
#define DCR_FIFO_12_BYTE (UCHAR)0x60       // 12-byte FIFO threshhold
#define DCR_AUTO_INIT   (UCHAR)0x10        // Auto-init to remove packets from ring

// Constants for the NIC_INTR_MASK register.
// 
// Configure which ISR settings actually cause interrupts.
#define IMR_RCV         (UCHAR)0x01        // packet received with no errors
#define IMR_XMIT        (UCHAR)0x02        // packet transmitted with no errors
#define IMR_RCV_ERR     (UCHAR)0x04        // error on packet reception
#define IMR_XMIT_ERR    (UCHAR)0x08        // error on packet transmission
#define IMR_OVERFLOW    (UCHAR)0x10        // receive buffer overflow
#define IMR_COUNTER     (UCHAR)0x20        // MSB set on tally counter


// start the card
#define CardStart(pAdapter) \
    NdisRawWritePortUchar(((pAdapter->Info.IoPAddr)+NIC_XMIT_CONFIG), TCR_NO_LOOPBACK)



//  Reads the interrupt status (ISR) register from the card. Only// Arguments:
//  called at IRQL INTERRUPT_LEVEL.
//  InterruptStatus - Returns the value of ISR.
#define CardGetInterruptStatus(pAdapter,pInterruptStatus) \
    NdisRawReadPortUchar(((pAdapter)->Info.IoPAddr+NIC_INTR_STATUS),(pInterruptStatus))


// Blocks all interrupts from the card by clearing the interrupt mask (IMR) register.
// Only called from IRQL INTERRUPT_LEVEL.
#define CardBlockInterrupts(pAdapter) \
    NdisRawWritePortUchar((pAdapter->Info.IoPAddr+NIC_INTR_MASK), 0)


// Unblocks all interrupts from the card by setting the interrupt mask (IMR) register.
// Only called from IRQL INTERRUPT_LEVEL.
#define CardUnblockInterrupts(pAdapter) \
    NdisRawWritePortUchar((pAdapter->Info.IoPAddr+NIC_INTR_MASK),pAdapter->Info.NicInterruptMask)