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The following describes the current state of the NetWinder's floating pointemulator.In the following nomenclature is used to describe the floating pointinstructions. It follows the conventions in the ARM manual.<S|D|E> = <single|double|extended>, no default{P|M|Z} = {round to +infinity,round to -infinity,round to zero}, default = round to nearestNote: items enclosed in {} are optional.Floating Point Coprocessor Data Transfer Instructions (CPDT)------------------------------------------------------------LDF/STF - load and store floating<LDF|STF>{cond}<S|D|E> Fd, Rn<LDF|STF>{cond}<S|D|E> Fd, [Rn, #<expression>]{!}<LDF|STF>{cond}<S|D|E> Fd, [Rn], #<expression>These instructions are fully implemented.LFM/SFM - load and store multiple floatingForm 1 syntax:<LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn]<LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn, #<expression>]{!}<LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn], #<expression>Form 2 syntax:<LFM|SFM>{cond}<FD,EA> Fd, <count>, [Rn]{!}These instructions are fully implemented. They store/load three wordsfor each floating point register into the memory location given in the instruction. The format in memory is unlikely to be compatible withother implementations, in particular the actual hardware. Specificmention of this is made in the ARM manuals. Floating Point Coprocessor Register Transfer Instructions (CPRT)----------------------------------------------------------------Conversions, read/write status/control register instructionsFLT{cond}<S,D,E>{P,M,Z} Fn, Rd Convert integer to floating pointFIX{cond}{P,M,Z} Rd, Fn Convert floating point to integerWFS{cond} Rd Write floating point status registerRFS{cond} Rd Read floating point status registerWFC{cond} Rd Write floating point control registerRFC{cond} Rd Read floating point control registerFLT/FIX are fully implemented.RFS/WFS are fully implemented.RFC/WFC are fully implemented. RFC/WFC are supervisor only instructions, andpresently check the CPU mode, and do an invalid instruction trap if not calledfrom supervisor mode.Compare instructionsCMF{cond} Fn, Fm Compare floatingCMFE{cond} Fn, Fm Compare floating with exceptionCNF{cond} Fn, Fm Compare negated floatingCNFE{cond} Fn, Fm Compare negated floating with exceptionThese are fully implemented.Floating Point Coprocessor Data Instructions (CPDT)---------------------------------------------------Dyadic operations:ADF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - addSUF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - subtractRSF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse subtractMUF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - multiplyDVF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - divideRDV{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse divideThese are fully implemented.FML{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast multiplyFDV{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast divideFRD{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast reverse divideThese are fully implemented as well. They use the same algorithm as thenon-fast versions. Hence, in this implementation their performance isequivalent to the MUF/DVF/RDV instructions. This is acceptable accordingto the ARM manual. The manual notes these are defined only for singleoperands, on the actual FPA11 hardware they do not work for double orextended precision operands. The emulator currently does not checkthe requested permissions conditions, and performs the requested operation.RMF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - IEEE remainderThis is fully implemented.Monadic operations:MVF{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - moveMNF{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - move negatedThese are fully implemented.ABS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - absolute valueSQT{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - square rootRND{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - roundThese are fully implemented.URD{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - unnormalized roundNRM{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - normalizeThese are implemented. URD is implemented using the same code as the RNDinstruction. Since URD cannot return a unnormalized number, NRM becomesa NOP.Library calls:POW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - powerRPW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse powerPOL{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - polar angle (arctan2)LOG{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base 10LGN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base e EXP{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - exponentSIN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - sineCOS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - cosineTAN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - tangentASN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arcsineACS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arccosineATN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arctangentThese are not implemented. They are not currently issued by the compiler,and are handled by routines in libc. These are not implemented by the FPA11hardware, but are handled by the floating point support code. They should be implemented in future versions.Signalling:Signals are implemented. However current ELF kernels produced by Rebel.comhave a bug in them that prevents the module from generating a SIGFPE. Thisis caused by a failure to alias fp_current to the kernel variablecurrent_set[0] correctly.The kernel provided with this distribution (vmlinux-nwfpe-0.93) containsa fix for this problem and also incorporates the current version of theemulator directly. It is possible to run with no floating point moduleloaded with this kernel. It is provided as a demonstration of the technology and for those who want to do floating point work that dependson signals. It is not strictly necessary to use the module.A module (either the one provided by Russell King, or the one in this distribution) can be loaded to replace the functionality of the emulatorbuilt into the kernel.
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