sgihpc.h

microwindows移植到S3C44B0的源码

	/* The SEEQ hpc3 ethernet dma/control registers. */
	struct hpc3_ethregs ethregs;

	/* Here are where the hpc3 fifo's can be directly accessed
	 * via PIO accesses.  Under normal operation we never stick
	 * our grubby paws in here so it's just padding.
	 */
	char _unused1[PAGE_SIZE * 24];

	/* HPC3 irq status regs.  Due to a peculiar bug you need to
	 * look at two different register addresses to get at all of
	 * the status bits.  The first reg can only reliably report
	 * bits 4:0 of the status, and the second reg can only
	 * reliably report bits 9:5 of the hpc3 irq status.  I told
	 * you it was a peculiar bug. ;-)
	 */
	hpcreg istat0;		/* Irq status, only bits <4:0> reliable. */

#define HPC3_ISTAT_PBIMASK	0x0ff	/* irq bits for pbus devs 0 --> 7 */
#define HPC3_ISTAT_SC0MASK	0x100	/* irq bit for scsi channel 0 */
#define HPC3_ISTAT_SC1MASK	0x200	/* irq bit for scsi channel 1 */

	hpcreg gio64_misc;	/* GIO64 misc control bits. */
#define HPC3_GIOMISC_ERTIME	0x1	/* Enable external timer real time. */
#define HPC3_GIOMISC_DENDIAN	0x2	/* dma descriptor endian, 1=lit 0=big */

	hpcreg eeprom_data;	/* EEPROM data reg. */
#define HPC3_EEPROM_EPROT	0x01	/* Protect register enable */
#define HPC3_EEPROM_CSEL	0x02	/* Chip select */
#define HPC3_EEPROM_ECLK	0x04	/* EEPROM clock */
#define HPC3_EEPROM_DATO	0x08	/* Data out */
#define HPC3_EEPROM_DATI	0x10	/* Data in */

	hpcreg istat1;		/* Irq status, only bits <9:5> reliable. */
	hpcreg gio64_estat;	/* GIO64 error interrupt status reg. */
#define HPC3_GIOESTAT_BLMASK	0x000ff	/* Bus lane where bad parity occurred */
#define HPC3_GIOESTAT_CTYPE	0x00100	/* Bus cycle type, 0=PIO 1=DMA */
#define HPC3_GIOESTAT_PIDMSK	0x3f700	/* DMA channel parity identifier */

	/* Now direct PIO per-HPC3 peripheral access to external regs. */
	char _unused2[0x13fec];	/* Trust me... */
	hpcreg scsi0_ext[256];	/* SCSI channel 0 external regs */
	char _unused3[0x07c00];	/* Trust me... */
	hpcreg scsi1_ext[256];	/* SCSI channel 1 external regs */
	char _unused4[0x07c00];	/* It'll only hurt a little... */

	/* Ethernet external registers. Noone use them so we need some 
	 * padding instead.
	 */
	char _unused5[0x04000]; /* It'll hurt a lot if you leave this out */

	/* Per-peripheral device external registers and dma/pio control. */
	hpcreg pbus_extregs[16][256];	/* 2nd indice indexes controller */
	hpcreg pbus_dmacfgs[8][128];	/* 2nd indice indexes controller */
#define HPC3_PIODCFG_D3R    0x00000001	/* Cycles to spend in D3 for reads */
#define HPC3_PIODCFG_D4R    0x0000001e	/* Cycles to spend in D4 for reads */
#define HPC3_PIODCFG_D5R    0x000001e0	/* Cycles to spend in D5 for reads */
#define HPC3_PIODCFG_D3W    0x00000200	/* Cycles to spend in D3 for writes */
#define HPC3_PIODCFG_D4W    0x00003c00	/* Cycles to spend in D4 for writes */
#define HPC3_PIODCFG_D5W    0x0003c000	/* Cycles to spend in D5 for writes */
#define HPC3_PIODCFG_HWORD  0x00040000	/* Enable 16-bit dma access mode */
#define HPC3_PIODCFG_EHI    0x00080000	/* Places halfwords on high 16 bits of bus */
#define HPC3_PIODCFG_RTIME  0x00200000	/* Make this device real time on GIO bus */
#define HPC3_PIODCFG_BURST  0x07c00000	/* 5 bit burst count for DMA device */
#define HPC3_PIODCFG_DRQLV  0x08000000	/* Use live pbus_dreq unsynchronized signal */

	hpcreg pbus_piocfgs[64][10];	/* 2nd indice indexes controller */
#define HPC3_PIOPCFG_RP2    0x00001	/* Cycles to spend in P2 state for reads */
#define HPC3_PIOPCFG_RP3    0x0001e	/* Cycles to spend in P3 state for reads */
#define HPC3_PIOPCFG_RP4    0x001e0	/* Cycles to spend in P4 state for reads */
#define HPC3_PIOPCFG_WP2    0x00200	/* Cycles to spend in P2 state for writes */
#define HPC3_PIOPCFG_WP3    0x03c00	/* Cycles to spend in P3 state for writes */
#define HPC3_PIOPCFG_WP4    0x3c000	/* Cycles to spend in P4 state for writes */
#define HPC3_PIOPCFG_HW     0x40000	/* Enable 16-bit PIO accesses */
#define HPC3_PIOPCFG_EHI    0x80000	/* Place even address bits in bits <15:8> */

	/* PBUS PROM control regs. */
	hpcreg pbus_promwe;	/* PROM write enable register */
#define HPC3_PROM_WENAB	    0x1	/* Enable writes to the PROM */

	char _unused6[0x800 - sizeof(hpcreg)];
	hpcreg pbus_promswap;	/* Chip select swap reg */
#define HPC3_PROM_SWAP      0x1	/* invert GIO addr bit to select prom0 or prom1 */

	char _unused7[0x800 - sizeof(hpcreg)];
	hpcreg pbus_gout;	/* PROM general purpose output reg */
#define HPC3_PROM_STAT      0x1	/* General purpose status bit in gout */

	char _unused8[0x1000 - sizeof(hpcreg)];
	hpcreg pbus_promram[16384];	/* 64k of PROM battery backed ram */
};

/* It is possible to have two HPC3's within the address space on
 * one machine, though only having one is more likely on an INDY.
 * Controller 0 lives at physical address 0x1fb80000 and the controller
 * 1 if present lives at address 0x1fb00000.
 */
extern struct hpc3_regs *hpc3c0, *hpc3c1;
#define HPC3_CHIP0_PBASE	0x1fb80000	/* physical */
#define HPC3_CHIP1_PBASE	0x1fb00000	/* physical */

/* Control and misc status information, these live in pbus channel 6. */
struct hpc3_miscregs {
	hpcreg pdata, pctrl, pstat, pdmactrl, pistat, pimask;
	hpcreg ptimer1, ptimer2, ptimer3, ptimer4;
	hpcreg _unused1[2];
	hpcreg ser1cmd, ser1data;
	hpcreg ser0cmd, ser0data;
	hpcreg kbdmouse0, kbdmouse1;
	hpcreg gcsel, genctrl, panel;
	hpcreg _unused2;
	hpcreg sysid;
	hpcreg _unused3;
	hpcreg read, _unused4;
	hpcreg dselect;
#define HPC3_DSELECT_SCLK10MHZ	0x00	/* use 10MHZ serial clock */
#define HPC3_DSELECT_ISDNB	0x01	/* enable isdn B */
#define HPC3_DSELECT_ISDNA	0x02	/* enable isdn A */
#define HPC3_DSELECT_LPR	0x04	/* use parallel DMA */
#define HPC3_DSELECT_SCLK667MHZ	0x10	/* use 6.67MHZ serial clock */
#define HPC3_DSELECT_SCLKEXT	0x20	/* use external serial clock */

	hpcreg _unused5;
	hpcreg write1;
#define HPC3_WRITE1_PRESET	0x01	/* 0=LPR_RESET, 1=NORMAL */
#define HPC3_WRITE1_KMRESET	0x02	/* 0=KBDMOUSE_RESET, 1=NORMAL */
#define HPC3_WRITE1_ERESET	0x04	/* 0=EISA_RESET, 1=NORMAL */
#define HPC3_WRITE1_GRESET	0x08	/* 0=MAGIC_GIO_RESET, 1=NORMAL */
#define HPC3_WRITE1_LC0OFF	0x10	/* turn led off (guiness=red, else green) */
#define HPC3_WRITE1_LC1OFF	0x20	/* turn led off (guiness=green, else amber) */

	hpcreg _unused6;
	hpcreg write2;
#define HPC3_WRITE2_NTHRESH	0x01	/* use 4.5db threshhold */
#define HPC3_WRITE2_TPSPEED	0x02	/* use 100ohm TP speed */
#define HPC3_WRITE2_EPSEL	0x04	/* force cable mode: 1=AUI 0=TP */
#define HPC3_WRITE2_EASEL	0x08	/* 1=autoselect 0=manual cable selection */
#define HPC3_WRITE2_U1AMODE	0x10	/* 1=PC 0=MAC UART mode */
#define HPC3_WRITE2_U0AMODE	0x20	/* 1=PC 0=MAC UART mode */
#define HPC3_WRITE2_MLO		0x40	/* 1=4.75V 0=+5V */
#define HPC3_WRITE2_MHI		0x80	/* 1=5.25V 0=+5V */
};
extern struct hpc3_miscregs *hpc3mregs;
#define HPC3_MREGS_PBASE	0x1fbd9800	/* physical */

/* We need software copies of these because they are write only. */
extern unsigned int sgi_hpc_write1, sgi_hpc_write2;

struct hpc_keyb {
#ifdef __MIPSEB__
	unsigned char _unused0[3];
	volatile unsigned char data;
	unsigned char _unused1[3];
	volatile unsigned char command;
#else
	volatile unsigned char data;
	unsigned char _unused0[3];
	volatile unsigned char command;
	unsigned char _unused1[3];
#endif
};

/* Indy RTC  */

/* The layout of registers for the INDY Dallas 1286 clock chipset. */
struct indy_clock {
	volatile unsigned int hsec;
	volatile unsigned int sec;
	volatile unsigned int min;
	volatile unsigned int malarm;
	volatile unsigned int hr;
	volatile unsigned int halarm;
	volatile unsigned int day;
	volatile unsigned int dalarm;
	volatile unsigned int date;
	volatile unsigned int month;
	volatile unsigned int year;
	volatile unsigned int cmd;
	volatile unsigned int whsec;
	volatile unsigned int wsec;
	volatile unsigned int _unused0[50];
};

#define INDY_CLOCK_REGS (KSEG1ADDR(0x1fbe0000))

extern void sgihpc_init(void);

#endif /* __ASM_SGI_SGIHPC_H */