sbmips.h

microwindows移植到S3C44B0的源码

#define CSR_SU		0x00000008
#define CSR_SI		0x00000004
#define CSR_RM		0x00000003

/* Status Register */
#define M_SR_CUMASK	_MM_MAKEMASK(4,28)	/* coprocessor usable bits */
#define M_SR_CU3	_MM_MAKEMASK1(31)	/* coprocessor 3 usable */
#define M_SR_CU2	_MM_MAKEMASK1(30)	/* coprocessor 2 usable */
#define M_SR_CU1	_MM_MAKEMASK1(29)	/* coprocessor 1 usable */
#define M_SR_CU0	_MM_MAKEMASK1(28)	/* coprocessor 0 usable */

#define M_SR_RP		_MM_MAKEMASK1(27)	/* reduced power mode */
#define M_SR_FR		_MM_MAKEMASK1(26)	/* fpu regs any data */
#define M_SR_RE		_MM_MAKEMASK1(25)	/* reverse endian */
#define M_SR_MX		_MM_MAKEMASK1(24)	/* MDMX */
#define M_SR_PX		_MM_MAKEMASK1(23)	/* 64-bit ops in user mode */
#define M_SR_BEV	_MM_MAKEMASK1(22)	/* boot exception vectors */
#define M_SR_TS		_MM_MAKEMASK1(21)	/* TLB is shut down */
#define M_SR_SR		_MM_MAKEMASK1(20)	/* soft reset */
#define M_SR_NMI	_MM_MAKEMASK1(19)	/* nonmaskable interrupt */

#define M_SR_IMASK	_MM_MAKEMASK(8,8)	/* all interrupt mask bits */

#define M_SR_IBIT8	_MM_MAKEMASK1(15)	/* individual bits */
#define M_SR_IBIT7	_MM_MAKEMASK1(14)
#define M_SR_IBIT6	_MM_MAKEMASK1(13)
#define M_SR_IBIT5	_MM_MAKEMASK1(12)
#define M_SR_IBIT4	_MM_MAKEMASK1(11)
#define M_SR_IBIT3	_MM_MAKEMASK1(10)
#define M_SR_IBIT2	_MM_MAKEMASK1(9)
#define M_SR_IBIT1	_MM_MAKEMASK1(8)

#define M_SR_IMASK8	0			/* masks for nested int levels */
#define M_SR_IMASK7	_MM_MAKEMASK(1,15)
#define M_SR_IMASK6	_MM_MAKEMASK(2,14)
#define M_SR_IMASK5	_MM_MAKEMASK(3,13)
#define M_SR_IMASK4	_MM_MAKEMASK(4,12)
#define M_SR_IMASK3	_MM_MAKEMASK(5,11)
#define M_SR_IMASK2	_MM_MAKEMASK(6,10)
#define M_SR_IMASK1	_MM_MAKEMASK(7,9)
#define M_SR_IMASK0	_MM_MAKEMASK(8,8)

#define M_SR_KX		_MM_MAKEMASK1(7)	/* 64-bit access for kernel */
#define M_SR_SX		_MM_MAKEMASK1(6)	/* .. for supervisor */
#define M_SR_UX		_MM_MAKEMASK1(5)	/* .. for user */

#define S_SR_KSU	3			/* base operating mode mode */
#define M_SR_KSU	_MM_MAKEMASK(2,S_SR_KSU)
#define V_SR_KSU(x)	_MM_MAKEVALUE(x,S_SR_KSU)
#define G_SR_KSU(x)	_MM_GETVALUE(x,S_SR_KSU,M_SR_KSU)
#define K_SR_KSU_KERNEL	0
#define K_SR_KSU_SUPR	1
#define K_SR_KSU_USER	2

#define M_SR_UM		_MM_MAKEMASK1(4)
#define M_SR_ERL	_MM_MAKEMASK1(2)
#define M_SR_EXL	_MM_MAKEMASK1(1)
#define M_SR_IE		_MM_MAKEMASK1(0)

/* 
 * Cause Register 
 */
#define M_CAUSE_BD	_MM_MAKEMASK1(31) /* exception in BD slot */

#define S_CAUSE_CE	28		/* coprocessor error */
#define M_CAUSE_CE	_MM_MAKEMASK(2,S_CAUSE_CE)
#define V_CAUSE_CE(x)	_MM_MAKEVALUE(x,S_CAUSE_CE)
#define G_CAUSE_CE(x)	_MM_GETVALUE(x,S_CAUSE_CE,M_CAUSE_CE)

#define M_CAUSE_IV	_MM_MAKEMASK1(23) /* special interrupt */
#define M_CAUSE_WP      _MM_MAKEMASK1(22) /* watch interrupt deferred */

#define S_CAUSE_IPMASK	8
#define M_CAUSE_IPMASK	_MM_MAKEMASK(8,S_CAUSE_IPMASK)
#define M_CAUSE_IP8	_MM_MAKEMASK1(15)	/* hardware interrupts */
#define M_CAUSE_IP7	_MM_MAKEMASK1(14)
#define M_CAUSE_IP6	_MM_MAKEMASK1(13)
#define M_CAUSE_IP5	_MM_MAKEMASK1(12)
#define M_CAUSE_IP4	_MM_MAKEMASK1(11)
#define M_CAUSE_IP3	_MM_MAKEMASK1(10)
#define M_CAUSE_SW2	_MM_MAKEMASK1(9)	/* software interrupts */
#define M_CAUSE_SW1	_MM_MAKEMASK1(8)

#define S_CAUSE_EXC	2
#define M_CAUSE_EXC	_MM_MAKEMASK(5,S_CAUSE_EXC)
#define V_CAUSE_EXC(x)	_MM_MAKEVALUE(x,S_CAUSE_EXC)
#define G_CAUSE_EXC(x)	_MM_GETVALUE(x,S_CAUSE_EXC,M_CAUSE_EXC)

/* Exception Code */
#define K_CAUSE_EXC_INT		0	/* External interrupt */
#define K_CAUSE_EXC_MOD		1	/* TLB modification */
#define K_CAUSE_EXC_TLBL	2    	/* TLB miss (Load or Ifetch) */
#define K_CAUSE_EXC_TLBS	3	/* TLB miss (Save) */
#define K_CAUSE_EXC_ADEL	4    	/* Address error (Load or Ifetch) */
#define K_CAUSE_EXC_ADES	5	/* Address error (Save) */
#define K_CAUSE_EXC_IBE		6	/* Bus error (Ifetch) */
#define K_CAUSE_EXC_DBE		7	/* Bus error (data load or store) */
#define K_CAUSE_EXC_SYS		8	/* System call */
#define K_CAUSE_EXC_BP		9	/* Break point */
#define K_CAUSE_EXC_RI		10	/* Reserved instruction */
#define K_CAUSE_EXC_CPU		11	/* Coprocessor unusable */
#define K_CAUSE_EXC_OVF		12	/* Arithmetic overflow */
#define K_CAUSE_EXC_TRAP	13	/* Trap exception */
#define K_CAUSE_EXC_VCEI	14	/* Virtual Coherency Exception (I) */
#define K_CAUSE_EXC_FPE		15	/* Floating Point Exception */
#define K_CAUSE_EXC_CP2		16	/* Cp2 Exception */
#define K_CAUSE_EXC_WATCH	23	/* Watchpoint exception */
#define K_CAUSE_EXC_VCED	31	/* Virtual Coherency Exception (D) */

#define	K_NTLBENTRIES	64

#define HI_HALF(x)	((x) >> 16)
#define LO_HALF(x)	((x) & 0xffff)

/* FPU stuff */

#if defined(__ASSEMBLY__)
#define C1_CSR		$31
#define C1_FRID		$0
#else
#define C1_CSR		31
#define C1_FRID		0
#endif

#define S_FCSR_CAUSE	12
#define M_FCSR_CAUSE	_MM_MAKEMASK(5,S_FCSR_CAUSE)
#define V_FCSR_CAUSE(x)	_MM_MAKEVALUE(x,S_FCSR_CAUSE)
#define G_FCSR_CAUSE(x)	_MM_GETVALUE(x,S_FCSR_CAUSE,M_FCSR_CAUSE)

#define S_FCSR_ENABLES	7
#define M_FCSR_ENABLES	_MM_MAKEMASK(5,S_FCSR_ENABLES)
#define V_FCSR_ENABLES(x) _MM_MAKEVALUE(x,S_FCSR_ENABLES)
#define G_FCSR_ENABLES(x) _MM_GETVALUE(x,S_FCSR_ENABLES,M_FCSR_ENABLES)

#define S_FCSR_FLAGS	2
#define M_FCSR_FLAGS	_MM_MAKEMASK(5,S_FCSR_FLAGS)
#define V_FCSR_FLAGS(x)	_MM_MAKEVALUE(x,S_FCSR_FLAGS)
#define G_FCSR_FLAGS(x)	_MM_GETVALUE(x,S_FCSR_FLAGS,M_FCSR_FLAGS)


/*
 * MIPS64 Config Register (select 0)
 */
#define M_CFG_CFG1	_MM_MAKEMASK1(31)	/* config1 select1 is impl */
#define M_CFG_BE        _MM_MAKEMASK1(15)	/* big-endian mode */

#define S_CFG_AT	13			/* Architecture Type */
#define M_CFG_AT	_MM_MAKEMASK(2,S_CFG_AT)
#define V_CFG_AT(x)	_MM_MAKEVALUE(x,S_CFG_AT)
#define G_CFG_AT(x)	_MM_GETVALUE(x,S_CFG_AT,M_CFG_AT)
#define K_CFG_AT_MIPS32	0
#define K_CFG_AT_MIPS64_32 1
#define K_CFG_AT_MIPS64	2

#define S_CFG_AR	10			/* Architecture Revision */
#define M_CFG_AR        _MM_MAKEMASK(3,S_CFG_AR)
#define V_CFG_AR(x)	_MM_MAKEVALUE(x,S_CFG_AR)
#define G_CFG_AR(x)	_MM_GETVALUE(x,S_CFG_AR,M_CFG_AR)
#define K_CFG_AR_REV1	0

#define S_CFG_MMU	7			/* MMU Type */
#define M_CFG_MMU       _MM_MAKEMASK(3,S_CFG_MMU)
#define V_CFG_MMU(x)	_MM_MAKEVALUE(x,S_CFG_MMU)
#define G_CFG_MMU(x)	_MM_GETVALUE(x,S_CFG_MMU,M_CFG_MMU)
#define K_CFG_MMU_NONE	0
#define K_CFG_MMU_TLB	1
#define K_CFG_MMU_BAT	2
#define K_CFG_MMU_FIXED	3

#define S_CFG_K0COH	0			/* K0seg coherency */
#define M_CFG_K0COH	_MM_MAKEMASK(3,S_CFG_K0COH)
#define V_CFG_K0COH(x)	_MM_MAKEVALUE(x,S_CFG_K0COH)
#define G_CFG_K0COH(x)	_MM_GETVALUE(x,S_CFG_K0COH,M_CFG_K0COH)
#define K_CFG_K0COH_UNCACHED	2
#define K_CFG_K0COH_CACHEABLE	3
#define K_CFG_K0COH_COHERENT	5

/*
 * MIPS64 Config Register (select 1)
 */

#define M_CFG_CFG2	_MM_MAKEMASK1(31)	/* config2 select2 is impl */

#define S_CFG_MMUSIZE	25
#define M_CFG_MMUSIZE	_MM_MAKEMASK(6,S_CFG_MMUSIZE)

#define S_CFG_IS	22
#define M_CFG_IS	_MM_MAKEMASK(3,S_CFG_IS)
#define V_CFG_IS(x)	_MM_MAKEVALUE(x,S_CFG_IS)
#define G_CFG_IS(x)	_MM_GETVALUE(x,S_CFG_IS,M_CFG_IS)

#define S_CFG_IL	19
#define M_CFG_IL	_MM_MAKEMASK(S_CFG_IL,3)
#define V_CFG_IL(x)	_MM_MAKEVALUE(x,S_CFG_IL)
#define G_CFG_IL(x)	_MM_GETVALUE(x,S_CFG_IL,M_CFG_IL)

#define S_CFG_IA	16
#define M_CFG_IA	_MM_MAKEMASK(3,S_CFG_IA)
#define V_CFG_IA(x)	_MM_MAKEVALUE(x,S_CFG_IA)
#define G_CFG_IA(x)	_MM_GETVALUE(x,S_CFG_IA,M_CFG_IA)

#define S_CFG_DS	13
#define M_CFG_DS	_MM_MAKEMASK(3,S_CFG_DS)
#define V_CFG_DS(x)	_MM_MAKEVALUE(x,S_CFG_DS)
#define G_CFG_DS(x)	_MM_GETVALUE(x,S_CFG_DS,M_CFG_DS)

#define S_CFG_DL	10
#define M_CFG_DL	_MM_MAKEMASK(3,S_CFG_DL)
#define V_CFG_DL(x)	_MM_MAKEVALUE(x,S_CFG_DL)
#define G_CFG_DL(x)	_MM_GETVALUE(x,S_CFG_DL,M_CFG_DL)

#define S_CFG_DA	7
#define M_CFG_DA	_MM_MAKEMASK(3,S_CFG_DA)
#define V_CFG_DA(x)	_MM_MAKEVALUE(x,S_CFG_DA)
#define G_CFG_DA(x)	_MM_GETVALUE(x,S_CFG_DA,M_CFG_DA)

#define M_CFG_PC	_MM_MAKEMASK1(4)	/* perf ctrs present */
#define M_CFG_WR	_MM_MAKEMASK1(3)	/* watch regs present */
#define M_CFG_CA	_MM_MAKEMASK1(2)	/* MIPS16 present */
#define M_CFG_EP	_MM_MAKEMASK1(1)	/* EJTAG present */
#define M_CFG_FP	_MM_MAKEMASK1(0)	/* FPU present */



/* 
 * Primary Cache TagLo 
 */

#define S_TAGLO_PTAG	8
#define M_TAGLO_PTAG 	_MM_MAKEMASK(56,S_TAGLO_PTAG)

#define S_TAGLO_PSTATE	6
#define M_TAGLO_PSTATE	_MM_MAKEMASK(2,S_TAGLO_PSTATE)
#define V_TAGLO_PSTATE(x) _MM_MAKEVALUE(x,S_TAGLO_PSTATE)
#define G_TAGLO_PSTATE(x) _MM_GETVALUE(x,S_TAGLO_PSTATE,M_TAGLO_PSTATE)
#define K_TAGLO_PSTATE_INVAL		0
#define K_TAGLO_PSTATE_SHARED		1
#define K_TAGLO_PSTATE_CLEAN_EXCL	2
#define K_TAGLO_PSTATE_DIRTY_EXCL	3

#define M_TAGLO_LOCK	_MM_MAKEMASK1(5)
#define M_TAGLO_PARITY	_MM_MAKEMASK1(0)


/*
 * CP0 CacheErr register
 */
#define M_CERR_DATA	_MM_MAKEMASK1(31)	/* err in D space */
#define M_CERR_SCACHE	_MM_MAKEMASK1(30)	/* err in l2, not l1 */
#define M_CERR_DERR	_MM_MAKEMASK1(29)	/* data error */
#define M_CERR_TERR	_MM_MAKEMASK1(28)	/* tag error */
#define M_CERR_EXTRQ	_MM_MAKEMASK1(27)	/* external req caused err */
#define M_CERR_BPAR	_MM_MAKEMASK1(26)	/* bus parity err */
#define M_CERR_ADATA	_MM_MAKEMASK1(25)	/* additional data */
#define M_CERR_IDX	_MM_MAKEMASK(22,0)



/*
 * Primary Cache operations
 */
#define Index_Invalidate_I               0x0         /* 0       0 */
#define Index_Writeback_Inv_D            0x1         /* 0       1 */
#define Index_Invalidate_SI              0x2         /* 0       2 */
#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
#define Index_Load_Tag_I                 0x4         /* 1       0 */
#define Index_Load_Tag_D                 0x5         /* 1       1 */
#define Index_Load_Tag_SI                0x6         /* 1       2 */
#define Index_Load_Tag_SD                0x7         /* 1       3 */
#define Index_Store_Tag_I                0x8         /* 2       0 */
#define Index_Store_Tag_D                0x9         /* 2       1 */
#define Index_Store_Tag_SI               0xA         /* 2       2 */
#define Index_Store_Tag_SD               0xB         /* 2       3 */
#define Create_Dirty_Exc_D               0xD         /* 3       1 */
#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
#define Hit_Invalidate_I                 0x10        /* 4       0 */
#define Hit_Invalidate_D                 0x11        /* 4       1 */
#define Hit_Invalidate_SI                0x12        /* 4       2 */
#define Hit_Invalidate_SD                0x13        /* 4       3 */
#define Fill_I                           0x14        /* 5       0 */
#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
#define Hit_Writeback_I                  0x18        /* 6       0 */
#define Hit_Writeback_D                  0x19        /* 6       1 */
#define Hit_Writeback_SD                 0x1B        /* 6       3 */
#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */

/* Watchpoint Register */
#define M_WATCH_PA		0xfffffff8
#define M_WATCH_R		0x00000002
#define M_WATCH_W		0x00000001


/* TLB entries */
#define M_TLBHI_ASID		_MM_MAKEMASK(0,8)
#define M_TLBHI_VPN2		_MM_MAKEMASK(27,13)

#define M_TLBLO_G		_MM_MAKEMASK1(0)
#define M_TLBLO_V		_MM_MAKEMASK1(1)
#define M_TLBLO_D		_MM_MAKEMASK1(2)

#define S_TLBLO_CALG		3
#define M_TLBLO_CALG		_MM_MAKEMASK(3,S_TLBLO_CALG)
#define V_TLBLO_CALG(x) 	_MM_MAKEVALUE(x,S_TLBLO_CALG)
#define G_TLBLO_CALG(x) 	_MM_GETVALUE(x,S_TLBLO_CALG,M_TLBLO_CALG)

#define K_CALG_COH_EXCL1_NOL2	0
#define K_CALG_COH_SHRL1_NOL2	1
#define K_CALG_UNCACHED		2
#define K_CALG_NONCOHERENT	3
#define K_CALG_COH_EXCL		4
#define K_CALG_COH_SHAREABLE	5
#define K_CALG_NOTUSED		6
#define K_CALG_UNCACHED_ACCEL	7

#define S_TLBLO_PFNMASK		6
#define M_TLBLO_PFNMASK		_MM_MAKEMASK(24,S_TLBLO_PFNMASK)
#define V_TLBLO_PFNMASK(x) 	_MM_MAKEVALUE(x,S_TLBLO_PFNMASK)
#define G_TLBLO_PFNMASK(x) 	_MM_GETVALUE(x,S_TLBLO_PFNMASK,M_TLBLO_PFNMASK)



#endif /* _SB_MIPS_H */