entry-armv.s

microwindows移植到S3C44B0的源码

#error INTSR stride != INTMR stride
#endif

		.macro	get_irqnr_and_base, irqnr, stat, base, mask
		mov	\base, #CLPS7111_BASE
		ldr	\stat, [\base, #INTSR1]
		ldr	\mask, [\base, #INTMR1]
		mov	\irqnr, #4
		mov	\mask, \mask, lsl #16
		and	\stat, \stat, \mask, lsr #16
		movs	\stat, \stat, lsr #4
		bne	1001f

		add	\base, \base, #INTSR2 - INTSR1
		ldr	\stat, [\base, #INTSR1]
		ldr	\mask, [\base, #INTMR1]
		mov	\irqnr, #16
		mov	\mask, \mask, lsl #16
		and	\stat, \stat, \mask, lsr #16

1001:		tst	\stat, #255
		addeq	\irqnr, \irqnr, #8
		moveq	\stat, \stat, lsr #8
		tst	\stat, #15
		addeq	\irqnr, \irqnr, #4
		moveq	\stat, \stat, lsr #4
		tst	\stat, #3
		addeq	\irqnr, \irqnr, #2
		moveq	\stat, \stat, lsr #2
		tst	\stat, #1
		addeq	\irqnr, \irqnr, #1
		moveq	\stat, \stat, lsr #1
		tst	\stat, #1			@ bit 0 should be set
		.endm

		.macro	irq_prio_table
		.endm

#elif defined(CONFIG_ARCH_ANAKIN)

		.macro	disable_fiq
		.endm

		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
		mov	\base, #IO_BASE
		mov	\irqstat, #INTERRUPT_CONTROLLER
		ldr	\tmp, =anakin_irq_mask
		ldr	\irqstat, [\base, \irqstat]
		ldr	\tmp, [\tmp]
		ands	\irqstat, \irqstat, \tmp
		ldrne	\tmp, =anakin_active_irqs
		strne	\irqstat, [\tmp]
		movne	\irqnr, #IRQ_ANAKIN
		.endm

		.macro	irq_prio_table
		.ltorg
		.bss
ENTRY(anakin_irq_mask)
		.word	0
ENTRY(anakin_active_irqs)
		.space	4
		.text
		.endm

#elif defined(CONFIG_ARCH_CNXT)

		.macro	disable_fiq
		.endm


		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp

#ifdef CONFIG_ARCH_P52
	
		ldr	r4, =P52INT_STATUS_M	
		ldr	\irqstat, [r4]


		tst	\irqstat, #P52INT_MASK_TIMER_1 
		movne	\irqnr, #P52INT_LVL_TIMER_1
		bne	1001f
	
		tst	\irqstat, #P52INT_MASK_TIMER_2
		movne	\irqnr, #P52INT_LVL_TIMER_2
		bne	1001f

		tst	\irqstat, #P52INT_MASK_TIMER_3
		movne	\irqnr, #P52INT_LVL_TIMER_3
		bne	1001f

		tst	\irqstat, #P52INT_MASK_TIMER_4
		movne	\irqnr, #P52INT_LVL_TIMER_4
		bne	1001f

		tst	\irqstat, #P52INT_MASK_USB 
		movne	\irqnr, #P52INT_LVL_USB 
		bne	1001f

		tst	\irqstat, #P52INT_MASK_HOST
		movne	\irqnr, #P52INT_LVL_HOST
		bne	1001f

		tst	\irqstat, #P52INT_MASK_HOST_ERR
		movne	\irqnr, #P52INT_LVL_HOST_ERR
		bne	1001f
	
		tst	\irqstat, #P52INT_MASK_DMA8 
		movne	\irqnr, #P52INT_LVL_DMA8 
		bne	1001f

		tst	\irqstat, #P52INT_MASK_DMA6
		movne	\irqnr, #P52INT_LVL_DMA6
		bne     1001f
	
		tst	\irqstat, #P52INT_MASK_DMA5
		movne	\irqnr, #P52INT_LVL_DMA5
		bne	1001f

		tst	\irqstat, #P52INT_MASK_DMA4
		movne	\irqnr, #P52INT_LVL_DMA4
		bne	1001f
	
		tst	\irqstat, #P52INT_MASK_DMA3
		movne	\irqnr, #P52INT_LVL_DMA3
		bne	1001f

		tst	\irqstat, #P52INT_MASK_DMA2
		movne	\irqnr, #P52INT_LVL_DMA2
		bne	1001f

		tst	\irqstat, #P52INT_MASK_DMA1
		movne	\irqnr, #P52INT_LVL_DMA1
		bne	1001f

		tst	\irqstat, #P52INT_MASK_DMA_ERR 
		movne	\irqnr, #P52INT_LVL_DMA_ERR 
		bne	1001f

		tst	\irqstat, #P52INT_MASK_E2_ERR
		movne	\irqnr, #P52INT_LVL_E2_ERR
		bne	1001f
       
		tst	\irqstat, #P52INT_MASK_E1_ERR 
		movne	\irqnr, #P52INT_LVL_E1_ERR 
		bne	1001f

		tst	\irqstat, #P52INT_MASK_DSL
		movne	\irqnr, #P52INT_LVL_DSL
		bne	1001f

		tst	\irqstat, #P52INT_MASK_GPIO 
		movne	\irqnr, #P52INT_LVL_GPIO 
		bne	1001f

		tst	\irqstat, #P52INT_MASK_COMMTX
		movne	\irqnr, #P52INT_LVL_COMMTX
		bne	1001f

		tst	\irqstat, #P52INT_MASK_COMMRX
		movne	\irqnr, #P52INT_LVL_COMMRX
		bne	1001f

		tst	\irqstat, #P52INT_MASK_SW1 
		movne	\irqnr, #P52INT_LVL_SW1
		bne	1001f

		tst	\irqstat, #P52INT_MASK_SW2
		movne	\irqnr, #P52INT_LVL_SW2
		bne	1001f

		tst	\irqstat, #P52INT_MASK_SW3
		movne	\irqnr, #P52INT_LVL_SW3
		bne	1001f

		tst	\irqstat, #P52INT_MASK_SW4
		movne	\irqnr, #P52INT_LVL_SW4

	
1001:

#endif

		
#ifdef CONFIG_ARCH_SPIPE
		@
		@ not been tested 
		@	
		ldr	r4, =0x350044
		ldr	\irqnr, [r4]	
		
		mov r5,#0
icloopusr:
		cmp r5,#31
		ble icshftusr
		b icendusr
icshftusr:
		mov r4,r6,lsr r5		@ shift untill we get one
		and r0,r4,#1			@ int priority is in the status
		cmp r0,#0
		beq incicusr
		b icendusr
incicusr:
		add r5,r5,#1
		b icloopusr
		
icendusr:		 
		mov	r0, r5
#endif

		.endm

		.macro	irq_prio_table
		.endm
	
#elif defined(CONFIG_ARCH_ATMEL)

		.macro	disable_fiq
		.endm

		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
		ldr	r4, =AIC_IVR
		ldr	\irqnr, [r4]		@ignore value
		ldr	r4, =AIC_ISR		@read interrupt nr.
		ldr	\irqnr, [r4]
		teq	\irqnr, #0

		ldreq	r4, =AIC_EOICR		@ EOI
		streq	r4, [r4]		@ value=dont care
		.endm

		.macro	irq_prio_table
		.endm

#elif defined(CONFIG_ARCH_NETARM)
#include <asm/arch/netarm_gen_module.h>

		.macro	disable_fiq
		mrs	r13, spsr
		orr	r13, r13, #F_BIT
		msr	spsr_c, r13
		.endm

		.macro	get_irqnr_and_base, irqnr, stat, base, temp
		ldr 	\irqnr, =(NETARM_GEN_MODULE_BASE+NETARM_GEN_INTR_STATUS_EN)

		ldr	\base, [\irqnr, #0]	@ stash ISTATUS
		mov	\irqnr, #0
1001:		
		cmp	\base, #0		@ no flags set?
		beq	1002f			@ keep "eq" status when finishing!
		tst	\base, #1		@ lsb set?
		addeq	\irqnr, \irqnr, #1	@ if not, incr IRQ#
		moveq	\base, \base, LSR #1	@ r = r >> 1 
		beq	1001b

		cmp	\irqnr, #32		@ IRQ# too big?
		blge	_netarm_led_FAIL2
1002:
		adr	\base, irq_prio_netarm
		.endm
		
		.macro	irq_prio_table
irq_prio_netarm:
		.byte   0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
		.byte   16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
		.endm

#elif defined(CONFIG_ARCH_SAMSUNG)

		.macro disable_fiq
		.endm

		.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
		ldr	\base, =INTOSET_IRQ
		ldr	\irqnr, [\base]
		mov	\irqnr, \irqnr, lsr #2
		teq	\irqnr, #21
		.endm

		.macro irq_prio_table
		.endm

#elif defined(CONFIG_ARCH_S3C44B0)

		.macro disable_fiq
		.endm

		.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
		ldr	\base, =0x01e00020	@I_ISPR
		ldr	\base, [\base]
		mov	\irqnr, #0
2222:
		tst	\base, #1
		bne	1111f
		add	\irqnr, \irqnr, #1
		mov	\base, \base, lsr #1
		cmp	\irqnr, #26
		bcc	2222b
1111:
		.endm

		.macro irq_prio_table
		.endm

#elif defined(CONFIG_ARCH_SWARM)

		.macro  disable_fiq
		.endm

		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
		ldr     \irqstat, =SWARM_INT_IRQ_STATUS
		ldr     \irqstat, [\irqstat]            @ get interrupts

		mov     \irqnr, #0
1001:
		tst     \irqstat, #1
		bne     1002f
		add     \irqnr, \irqnr, #1
		mov     \irqstat, \irqstat, lsr #1
		cmp     \irqnr, #32
		bcc     1001b
1002:		/* EQ will be set if we reach 32 */
		.endm

		.macro  irq_prio_table
irq_prio_swarm:
		.byte   0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
		.endm

#else
#error Unknown architecture
#endif

/*
 * Invalid mode handlers
 */
__pabt_invalid:	sub	sp, sp, #S_FRAME_SIZE		@ Allocate frame size in one go
		stmia	sp, {r0 - lr}			@ Save XXX r0 - lr
		ldr	r4, .LCabt
		mov	r1, #BAD_PREFETCH
		b	1f

__dabt_invalid:	sub	sp, sp, #S_FRAME_SIZE
		stmia	sp, {r0 - lr}			@ Save SVC r0 - lr [lr *should* be intact]
		ldr	r4, .LCabt
		mov	r1, #BAD_DATA
		b	1f

__irq_invalid:	sub	sp, sp, #S_FRAME_SIZE		@ Allocate space on stack for frame
		stmfd	sp, {r0 - lr}			@ Save r0 - lr
		ldr	r4, .LCirq
		mov	r1, #BAD_IRQ
		b	1f

__und_invalid:	sub	sp, sp, #S_FRAME_SIZE
		stmia	sp, {r0 - lr}
		ldr	r4, .LCund
		mov	r1, #BAD_UNDEFINSTR		@ int reason

1:		zero_fp
		ldmia	r4, {r5 - r7}			@ Get XXX pc, cpsr, old_r0
		add	r4, sp, #S_PC
		stmia	r4, {r5 - r7}			@ Save XXX pc, cpsr, old_r0
		mov	r0, sp
		and	r2, r6, #31			@ int mode
		b	SYMBOL_NAME(bad_mode)

#if defined CONFIG_FPE_NWFPE || defined CONFIG_FPE_FASTFPE
		/* The FPE is always present */
		.equ	fpe_not_present, 0
#else
wfs_mask_data:	.word	0x0e200110			@ WFS/RFS
		.word	0x0fef0fff
		.word	0x0d000100			@ LDF [sp]/STF [sp]
		.word	0x0d000100			@ LDF [fp]/STF [fp]
		.word	0x0f000f00

/* We get here if an undefined instruction happens and the floating
 * point emulator is not present.  If the offending instruction was
 * a WFS, we just perform a normal return as if we had emulated the
 * operation.  This is a hack to allow some basic userland binaries
 * to run so that the emulator module proper can be loaded. --philb
 */
fpe_not_present:
		adr	r10, wfs_mask_data
		ldmia	r10, {r4, r5, r6, r7, r8}
		ldr	r10, [sp, #S_PC]		@ Load PC
		sub	r10, r10, #4
		mask_pc	r10, r10
		ldrt	r10, [r10]			@ get instruction
		and	r5, r10, r5
		teq	r5, r4				@ Is it WFS?
		moveq	pc, r9
		and	r5, r10, r8
		teq	r5, r6				@ Is it LDF/STF on sp or fp?
		teqne	r5, r7
		movne	pc, lr
		tst	r10, #0x00200000		@ Does it have WB
		moveq	pc, r9
		and	r4, r10, #255			@ get offset
		and	r6, r10, #0x000f0000
		tst	r10, #0x00800000		@ +/-
		ldr	r5, [sp, r6, lsr #14]		@ Load reg
		rsbeq	r4, r4, #0
		add	r5, r5, r4, lsl #2
		str	r5, [sp, r6, lsr #14]		@ Save reg
		mov	pc, r9
#endif

/*
 * SVC mode handlers
 */
		.align	5
__dabt_svc:	sub	sp, sp, #S_FRAME_SIZE
		stmia	sp, {r0 - r12}			@ save r0 - r12
		ldr	r2, .LCabt
		add	r0, sp, #S_FRAME_SIZE
		ldmia	r2, {r2 - r4}			@ get pc, cpsr
		add	r5, sp, #S_SP
		mov	r1, lr
		stmia	r5, {r0 - r4}			@ save sp_SVC, lr_SVC, pc, cpsr, old_ro
		mrs	r9, cpsr			@ Enable interrupts if they were
		tst	r3, #I_BIT
		biceq	r9, r9, #I_BIT			@ previously
		mov	r0, r2
/*
 * This routine must not corrupt r9
 */
#ifdef MULTI_CPU
		ldr	r2, .LCprocfns
		mov	lr, pc
		ldr	pc, [r2]			@ call processor specific code
#else
		bl	cpu_data_abort
#endif
		msr	cpsr_c, r9
		mov	r2, sp
		bl	SYMBOL_NAME(do_DataAbort)
		mrs	r0, cpsr
		bic	r0, r0, #MODE_MASK
		orr	r0, r0, #I_BIT | MODE_SVC	@ preserve FIQ bit
		msr	cpsr_c, r0
		ldr	r0, [sp, #S_PSR]
		msr	spsr, r0
		ldmia	sp, {r0 - pc}^			@ load r0 - pc, cpsr

		.align	5
__irq_svc:	sub	sp, sp, #S_FRAME_SIZE
		stmia	sp, {r0 - r12}			@ save r0 - r1
		ldr	r7, .LCirq
		add	r5, sp, #S_FRAME_SIZE
		ldmia	r7, {r7 - r9}
		add	r4, sp, #S_SP
		mov	r6, lr
		stmia	r4, {r5, r6, r7, r8, r9}	@ save sp_SVC, lr_SVC, pc, cpsr, old_ro
1:		get_irqnr_and_base r0, r6, r5, lr
		movne	r1, sp
		@
		@ routine called with r0 = irq number, r1 = struct pt_regs *
		@
		adrsvc	ne, lr, 1b
		bne	do_IRQ
		ldr	r0, [sp, #S_PSR]		@ irqs are already disabled
		msr	spsr, r0