proc-arm6,7.s

microwindows移植到S3C44B0的源码

 * Function: _arm6_7_reset
 * Params  : r0 = address to jump to
 * Notes   : This sets up everything for a reset
 */
ENTRY(cpu_arm6_reset)
ENTRY(cpu_arm7_reset)
		mov	r1, #0
#ifdef CONFIG_CPU_WITH_CACHE
# ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION
		mcr	p15, 0, r1, c7, c0, 0		@ flush cache
		mov	r1, #0x30
		mcr	p15, 0, r1, c1, c0, 0		@ turn off Cache etc
# else
#  warning		"FIXME: Flush and Disable cache without MCR Instruction"
#if defined(CONFIG_ARCH_S3C44B0)
		stmfd	sp!, {r0-r4}
                ldr     r2, =0x01c00000
                ldr     r4, =0x08
                str     r4, [r2]

                ldr     r3, =0x10002000
                add     r4, r3, #0x2800
        1:
                str     r0, [r3], #16
                teq     r3, r4
                bne     1b
		ldmfd	sp!, {r0-r4}
#endif        

# endif
#endif
#ifndef	NO_MM        
		mcr	p15, 0, r1, c5, c0, 0		@ flush TLB
		mov	r1, #0x30
		mcr	p15, 0, r1, c1, c0, 0		@ turn off MMU etc
#endif        
		mov	pc, r0

cpu_armvlsi_name:
		.asciz	"ARM/VLSI"
cpu_arm6_name:	.asciz	"ARM 6"
cpu_arm610_name:
		.asciz	"ARM 610"
cpu_arm7_name:	.asciz	"ARM 7"
cpu_arm710_name:
		.asciz	"ARM 710"
cpu_arm7tdmi_name:
		.asciz	"ARM 7 TDMI"
cpu_at91_manu_name:
		.asciz	"Atmel"
cpu_at91_name:
		.asciz	"AT91M40xxx"
cpu_s3c4510b_manu_name:
		.asciz	"Samsung"
cpu_s3c4510b_name:
		.asciz	"S3C4510B"
cpu_s3c44b0_manu_name:
		.asciz	"Samsung"
cpu_s3c44b0_name:
		.asciz	"S3C44B0"
		.align

		.section ".text.init", #alloc, #execinstr

__arm6_setup:	mov	r0, #F_BIT | I_BIT | SVC_MODE
		msr	cpsr_c, r0
		mov	r0, #0
#ifdef CONFIG_CPU_WITH_CACHE
# ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION
		mcr	p15, 0, r0, c7, c0		@ flush caches on v3
# else
#  warning		"FIXME: Flush cache without MCR Instruction"
#if defined(CONFIG_ARCH_S3C44B0)
		stmfd	sp!, {r0-r4}
                ldr     r2, =0x01c00000
                ldr     r1, [r2]
                ldr     r4, =0x08
                str     r4, [r2]

                ldr     r3, =0x10002000
                add     r4, r3, #0x2800
        1:
                str     r0, [r3], #16
                teq     r3, r4
                bne     1b

                str     r1, [r2]
		ldmfd	sp!, {r0-r4}
#endif        

# endif
#endif
#ifndef NO_MM
		mcr	p15, 0, r0, c5, c0		@ flush TLBs on v3
		mcr	p15, 0, r4, c2, c0		@ load page table pointer
		mov	r0, #0x1f			@ Domains 0, 1 = client
		mcr	p15, 0, r0, c3, c0		@ load domain access register
		mov	r0, #0x3d			@ ....S..DPWC.M
		orr	r0, r0, #0x100
#endif
#ifdef CONFIG_CPU_WITH_CACHE
# ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION
		mov	r0, #0x3c			@ .......DPWC..
# else 
#  warning		"FIXME: Enable Cache and Others without MCR Instruction"
#if defined(CONFIG_ARCH_S3C44B0)
		stmfd	sp!, {r0-r4}
                ldr     r2, =0x01c00000
                ldr     r0, =0x0e
                str     r0, [r2]
		ldmfd	sp!, {r0-r4}
#endif        

# endif
#else
		@ Just in case r0 is modified by any code above			
		mov	r0, #0x0			
# warning		"FIXME: Setup anything if required"
#endif
		mov	pc, lr

__arm7_setup:	mov	r0, #F_BIT | I_BIT | SVC_MODE
		msr	cpsr_c, r0
		mov	r0, #0
#ifdef CONFIG_CPU_WITH_CACHE
# ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION
		mcr	p15, 0, r0, c7, c0		@ flush caches on v3
# else
#  warning		"FIXME: Flush cache without MCR Instruction"
#if defined(CONFIG_ARCH_S3C44B0)
		stmfd	sp!, {r0-r4}
                ldr     r2, =0x01c00000
                ldr     r1, [r2]
                ldr     r4, =0x08
                str     r4, [r2]

                ldr     r3, =0x10002000
                add     r4, r3, #0x2800
        1:
                str     r0, [r3], #16
                teq     r3, r4
                bne     1b

                str     r1, [r2]
		ldmfd	sp!, {r0-r4}
#endif        

# endif
#endif
#ifndef	NO_MM        
		mcr	p15, 0, r0, c5, c0		@ flush TLBs on v3
		mcr	p15, 0, r4, c2, c0		@ load page table pointer
		mov	r0, #0x1f			@ Domains 0, 1 = client
		mcr	p15, 0, r0, c3, c0		@ load domain access register
		mov	r0, #0x7d			@ ....S.LDPWC.M
		orr	r0, r0, #0x100
#endif
#ifdef CONFIG_CPU_WITH_CACHE
# ifdef CONFIG_CPU_WITH_MCR_INSTRUCTION
		mov	r0, #0x7c			@ ......LDPWC..
# else 
#  warning		"FIXME: Enable Cache and Others without MCR Instruction"
#if defined(CONFIG_ARCH_S3C44B0)
		stmfd	sp!, {r0-r4}
                ldr     r2, =0x01c00000
                ldr     r0, =0x0e
                str     r0, [r2]
		ldmfd	sp!, {r0-r4}
#endif        

# endif
#else
		@ Just in case r0 is modified by any code above			
		mov	r0, #0x0			
# warning		"FIXME: Setup anything if required"
#endif
		mov	pc, lr

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
		.type	arm6_processor_functions, #object
ENTRY(arm6_processor_functions)
		.word	cpu_arm6_data_abort
		.word	cpu_arm6_check_bugs
		.word	cpu_arm6_proc_init
		.word	cpu_arm6_proc_fin
		.word	cpu_arm6_reset
		.word	cpu_arm6_do_idle

		/* cache */
		.word	cpu_arm6_cache_clean_invalidate_all
		.word	cpu_arm6_cache_clean_invalidate_range
		.word	cpu_arm6_flush_ram_page

		/* dcache */
		.word	cpu_arm6_dcache_invalidate_range
		.word	cpu_arm6_dcache_clean_range
		.word	cpu_arm6_dcache_clean_page
		.word	cpu_arm6_dcache_clean_entry

		/* icache */
		.word	cpu_arm6_icache_invalidate_range
		.word	cpu_arm6_icache_invalidate_page

		/* tlb */
		.word	cpu_arm6_tlb_invalidate_all
		.word	cpu_arm6_tlb_invalidate_range
		.word	cpu_arm6_tlb_invalidate_page

		/* pgtable */
		.word	cpu_arm6_set_pgd
		.word	cpu_arm6_set_pmd
		.word	cpu_arm6_set_pte
		.size	arm6_processor_functions, . - arm6_processor_functions

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
		.type	arm7_processor_functions, #object
ENTRY(arm7_processor_functions)
		.word	cpu_arm7_data_abort
		.word	cpu_arm7_check_bugs
		.word	cpu_arm7_proc_init
		.word	cpu_arm7_proc_fin
		.word	cpu_arm7_reset
		.word	cpu_arm7_do_idle

		/* cache */
		.word	cpu_arm7_cache_clean_invalidate_all
		.word	cpu_arm7_cache_clean_invalidate_range
		.word	cpu_arm7_flush_ram_page

		/* dcache */
		.word	cpu_arm7_dcache_invalidate_range
		.word	cpu_arm7_dcache_clean_range
		.word	cpu_arm7_dcache_clean_page
		.word	cpu_arm7_dcache_clean_entry

		/* icache */
		.word	cpu_arm7_icache_invalidate_range
		.word	cpu_arm7_icache_invalidate_page

		/* tlb */
		.word	cpu_arm7_tlb_invalidate_all
		.word	cpu_arm7_tlb_invalidate_range
		.word	cpu_arm7_tlb_invalidate_page

		/* pgtable */
		.word	cpu_arm7_set_pgd
		.word	cpu_arm7_set_pmd
		.word	cpu_arm7_set_pte
		.size	arm7_processor_functions, . - arm7_processor_functions

		.type	cpu_arm6_info, #object
cpu_arm6_info:
		.long	cpu_armvlsi_name
		.long	cpu_arm6_name
		.size	cpu_arm6_info, . - cpu_arm6_info

		.type	cpu_arm610_info, #object
cpu_arm610_info:
		.long	cpu_armvlsi_name
		.long	cpu_arm610_name
		.size	cpu_arm610_info, . - cpu_Arm610_info

		.type	cpu_arm7_info, #object
cpu_arm7_info:
		.long	cpu_armvlsi_name
		.long	cpu_arm7_name
		.size	cpu_arm7_info, . - cpu_arm7_info

		.type	cpu_arm7tdmi_info, #object
cpu_arm7tdmi_info:
		.long   cpu_armvlsi_name
		.long   cpu_arm7tdmi_name
		.size   cpu_arm7tdmi_info, . - cpu_arm7tdmi_info

		.type	cpu_at91_info, #object
cpu_at91_info:
		.long	cpu_at91_manu_name
		.long	cpu_at91_name
		.size	cpu_at91_info, . - cpu_at91_info

		.type	cpu_s3c4510b_info, #object
cpu_s3c4510b_info:
		.long	cpu_s3c4510b_manu_name
		.long	cpu_s3c4510b_name
		.size	cpu_s3c4510b_info, . - cpu_s3c4510b_info

		.type	cpu_s3c44b0_info, #object
cpu_s3c44b0_info:
		.long	cpu_s3c44b0_manu_name
		.long	cpu_s3c44b0_name
		.size	cpu_s3c44b0_info, . - cpu_s3c44b0_info

		.type	cpu_arm710_info, #object
cpu_arm710_info:
		.long	cpu_armvlsi_name
		.long	cpu_arm710_name
		.size	cpu_arm710_info, . - cpu_arm710_info

		.type	cpu_arch_name, #object
cpu_arch_name:	.asciz	"armv3"
		.size	cpu_arch_name, . - cpu_arch_name

		.type	cpu_elf_name, #object
cpu_elf_name:	.asciz	"v3"
		.size	cpu_elf_name, . - cpu_elf_name

		.align
		.section ".proc.info", #alloc, #execinstr

		.type	__arm6_proc_info, #object
__arm6_proc_info:
		.long	0x41560600
		.long	0xfffffff0
		.long	0x00000c1e
		b	__arm6_setup
		.long	cpu_arch_name
		.long	cpu_elf_name
		.long	HWCAP_SWP | HWCAP_26BIT
		.long	cpu_arm6_info
		.long	arm6_processor_functions
		.size	__arm6_proc_info, . - __arm6_proc_info

		.type	__arm610_proc_info, #object
__arm610_proc_info:
		.long	0x41560610
		.long	0xfffffff0
		.long	0x00000c1e
		b	__arm6_setup
		.long	cpu_arch_name
		.long	cpu_elf_name
		.long	HWCAP_SWP | HWCAP_26BIT
		.long	cpu_arm610_info
		.long	arm6_processor_functions
		.size	__arm610_proc_info, . - __arm610_proc_info

		.type	__arm7_proc_info, #object
__arm7_proc_info:
		.long	0x41007000
		.long	0xffffff00
		.long	0x00000c1e
		b	__arm7_setup
		.long	cpu_arch_name
		.long	cpu_elf_name
		.long	HWCAP_SWP | HWCAP_26BIT
		.long	cpu_arm7_info
		.long	arm7_processor_functions
		.size	__arm7_proc_info, . - __arm7_proc_info

		.type	__arm710_proc_info, #object
__arm710_proc_info:
		.long	0x41007100
		.long	0xfff8ff00
		.long	0x00000c1e
		b	__arm7_setup
		.long	cpu_arch_name
		.long	cpu_elf_name
		.long	HWCAP_SWP | HWCAP_26BIT
		.long	cpu_arm710_info
		.long	arm7_processor_functions
		.size	__arm710_proc_info, . - __arm710_proc_info

		.type	__arm7tdmi_proc_info, #object
__arm7tdmi_proc_info:
		.long	0x41007700
		.long	0xfff8ff00
		.long	0x00000c1e
		b	__arm7_setup
		.long	cpu_arch_name
		.long	cpu_elf_name
		.long	HWCAP_SWP | HWCAP_26BIT
		.long	cpu_arm7tdmi_info
		.long	arm7_processor_functions
		.size	__arm7tdmi_proc_info, . - __arm7tdmi_proc_info

		.type	__at91_proc_info, #object
__at91_proc_info:
		.long	0x14000040
		.long	0xfff000e0
		.long	0x00000c1e
		b	__arm7_setup
		.long	cpu_arch_name
		.long	cpu_elf_name
		.long	HWCAP_SWP | HWCAP_26BIT
		.long	cpu_at91_info
		.long	arm7_processor_functions
		.size	__at91_proc_info, . - __at91_proc_info

		.type	__s3c4510b_proc_info, #object
__s3c4510b_proc_info:
		.long	0x36365000			@ cpu_val
		.long	0xfffff000			@ cpu_mask
		.long	0x00000c1e			@ __cpu_mmu_flags
		b	__arm7_setup			@ __cpu_flush
		.long	cpu_arch_name			@ arch_name
		.long	cpu_elf_name			@ elf_name
		.long	HWCAP_SWP | HWCAP_26BIT		@ elf_hwcap
		.long	cpu_s3c4510b_info		@ info
		.long	arm7_processor_functions	@ info
		.size	__s3c4510b_proc_info, . - __s3c4510b_proc_info

		.type	__s3c44b0_proc_info, #object
__s3c44b0_proc_info:
                .long   0x07605781                      @ cpu_val
                .long   0x0fffffff                      @ cpu_mask
                .long   0x00000c1e                      @ __cpu_mmu_flags
                b       __arm7_setup                    @ __cpu_flush
                .long   cpu_arch_name                   @ arch_name
                .long   cpu_elf_name                    @ elf_name
                .long   HWCAP_SWP | HWCAP_26BIT         @ elf_hwcap
                .long   cpu_s3c44b0_info                @ info
                .long   arm7_processor_functions        @ info
                .size   __s3c44b0_proc_info, . - __s3c44b0_proc_info