crt0_ram.s

microwindows移植到S3C44B0的源码

/* arch/m68knommu/platform/68360/uCquicc/crt0_rom.S
 *
 * Startup code for Motorola 68360
 *
 * Copyright 2001 (C) SED Systems, a Division of Calian Ltd.
 * Based on: arch/m68knommu/platform/68328/pilot/crt0_rom.S
 * Based on: arch/m68knommu/platform/68360/uCquicc/crt0_rom.S, 2.0.38.1.pre7
 *           uClinux Kernel
 * Copyright (C) Michael Leslie <[e-mail]>
 * Based on: arch/m68knommu/platform/68EZ328/ucsimm/crt0_rom.S
 * Copyright (C) 1998  D. Jeff Dionne <[e-mail]>,
 *
 */
#define ASSEMBLY
#include <linux/config.h>

.global _stext
.global __bss_start
.global _start

.global _rambase
.global __ramvec
.global _ramvec
.global _ramstart
.global _ramend

.global _quicc_base
.global _periph_base
.global _dprbase

#define REGB                        0x1000
#define PEPAR                       (_dprbase + REGB + 0x0016)
#define GMR                         (_dprbase + REGB + 0x0040)
#define OR0                         (_dprbase + REGB + 0x0054)
#define BR0                         (_dprbase + REGB + 0x0050)
#define OR1                         (_dprbase + REGB + 0x0064)
#define BR1                         (_dprbase + REGB + 0x0060)
#define OR4                         (_dprbase + REGB + 0x0094)
#define BR4                         (_dprbase + REGB + 0x0090)
#define OR6                         (_dprbase + REGB + 0x00b4)
#define BR6                         (_dprbase + REGB + 0x00b0)
#define OR7                         (_dprbase + REGB + 0x00c4)
#define BR7                         (_dprbase + REGB + 0x00c0)

#define MCR                         (_dprbase + REGB + 0x0000)
#define AVR                         (_dprbase + REGB + 0x0008)

#define SYPCR                       (_dprbase + REGB + 0x0022)

#define PLLCR                       (_dprbase + REGB + 0x0010)
#define CLKOCR                      (_dprbase + REGB + 0x000C)
#define CDVCR                       (_dprbase + REGB + 0x0014)

#define BKAR                        (_dprbase + REGB + 0x0030)
#define BKCR                        (_dprbase + REGB + 0x0034)
#define SWIV                        (_dprbase + REGB + 0x0023)
#define PICR                        (_dprbase + REGB + 0x0026)
#define PITR                        (_dprbase + REGB + 0x002A)

/* Define for all memory configuration */
#define MCU_SIM_GMR                 0x00000000
#define SIM_OR_MASK                 0x0fffffff

/* Defines for chip select zero - the flash */
#define SIM_OR0_MASK                0x20000002
#define SIM_BR0_MASK                0x00000001


/* Defines for chip select one - the RAM */
#define SIM_OR1_MASK                0x10000000
#define SIM_BR1_MASK                0x00000001

#define MCU_SIM_MBAR_ADRS           0x0003ff00
#define MCU_SIM_MBAR_BA_MASK        0xfffff000
#define MCU_SIM_MBAR_AS_MASK        0x00000001

#define MCU_SIM_PEPAR               0x00B4
    
#define MCU_DISABLE_INTRPTS         0x2700
#define MCU_SIM_AVR                 0x00
    
#define MCU_SIM_MCR                 0x00005cff

#define MCU_SIM_CLKOCR              0x00
#define MCU_SIM_PLLCR               0x8000
#define MCU_SIM_CDVCR               0x0000

#define MCU_SIM_SYPCR               0x0000
#define MCU_SIM_SWIV                0x00
#define MCU_SIM_PICR                0x0000
#define MCU_SIM_PITR                0x0000


#include <asm/m68360_regs.h>

	
/* By the time this RAM specific code begins to execute, DPRAM
 * and DRAM should already be mapped and accessible. */

	.text
_start:
_stext:
    nop
    ori.w   #MCU_DISABLE_INTRPTS,   %sr     /* disable interrupts: */
    /* We should not need to setup the boot stack the reset should do it. */
    movea.l	#_boot_stack,           %sp     /*set up stack at the end of DRAM:*/


set_mbar_register:
    moveq.l #0x07,                  %d1     /* Setup MBAR */
    movec	%d1,                    %dfc

    lea.l   MCU_SIM_MBAR_ADRS,      %a0
    move.l  #_dprbase,              %d0
    andi.l  #MCU_SIM_MBAR_BA_MASK,  %d0
    ori.l   #MCU_SIM_MBAR_AS_MASK,  %d0
    moves.l %d0,                    %a0@

    moveq.l #0x05,                  %d1
    movec.l %d1,                    %dfc

/* Now we can begin to access registers in DPRAM */

set_sim_mcr:
    /* Set Module Configuration Register */
    move.l  #MCU_SIM_MCR,           MCR

/* to do:	Determine cause of reset */


    /*
    *       configure system clock MC68360 p. 6-40
    *       (value +1)*osc/128 = system clock
    */
set_sim_clock:
    move.w  #MCU_SIM_PLLCR,         PLLCR
    move.b  #MCU_SIM_CLKOCR,        CLKOCR
    move.w  #MCU_SIM_CDVCR,         CDVCR

    // Wait for the PLL to settle
    move.w      #16384, %d0
pll_settle_wait:
    subi.w       #1, %d0
    bne	pll_settle_wait

    /* Setup the system protection register, and watchdog timer register */

    move.b      #MCU_SIM_SWIV,      SWIV
    move.w      #MCU_SIM_PICR,      PICR
    move.w      #MCU_SIM_PITR,      PITR
    move.w      #MCU_SIM_SYPCR,     SYPCR

/* Clear DPRAM - system + parameter */
	movea.l	#_dprbase, %a0
	movea.l	#_dprbase+0x2000, %a1

	/* Copy 0 to %a0 until %a0 == %a1 */
clear_dpram:
	movel	#0, %a0@+
	cmpal	%a0, %a1
	bhi	clear_dpram

configure_memory_controller:    
    /*
    *   Set up Global Memory Register (GMR)
    */
    move.l      #MCU_SIM_GMR,   %d0
    move.l      %d0, GMR

configure_chip_select_0:
    move.l      #__ramend,      %d0
    subi.l      #__ramstart,    %d0
    subq.l      #0x01,          %d0
    eori.l      #SIM_OR_MASK,   %d0
    ori.l       #SIM_OR0_MASK,  %d0
    move.l      %d0,            OR0

    move.l      #__ramstart,    %d0
    ori.l       #SIM_BR0_MASK,  %d0
    move.l      %d0,            BR0


configure_chip_select_1:
    move.l      #__flashend,    %d0
    subi.l      #__flashstart,  %d0
    subq.l      #0x01,          %d0
    eori.l      #SIM_OR_MASK,   %d0
    ori.l       #SIM_OR1_MASK,  %d0
    move.l      %d0,            OR1

    move.l      #__flashstart,  %d0
    ori.l       #SIM_BR1_MASK,  %d0
    move.l      %d0,            BR1


    move.w      #MCU_SIM_PEPAR, PEPAR 

/* point to vector table: */
    move.l  #_romvec,   %a0
    move.l	#_ramvec,   %a1
copy_vectors:
    move.l  %a0@,       %d0
    move.l  %d0,        %a1@
    move.l  %a0@,       %a1@
    addq.l  #0x04,      %a0
    addq.l  #0x04,      %a1
    cmp.l   #_start,    %a0
    blt     copy_vectors