setup.c

microwindows移植到S3C44B0的源码

	/* IRQ routing. */
	memcpy(&dec_interrupt, &kn02_interrupt,
		sizeof(kn02_interrupt));

	/* CPU IRQ priorities. */
	memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
		sizeof(kn02_cpu_mask_nr_tbl));

	/* KN02 CSR IRQ priorities. */
	memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
		sizeof(kn02_asic_mask_nr_tbl));

	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
	init_kn02_irqs(KN02_IRQ_BASE);

}				/* dec_init_kn02 */


/*
 * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
 * (xx = 20, 25, 33), aka 3min.  Also applies to KN04(-BA), aka
 * DS5000/150, aka 4min.
 */
static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
	[DEC_IRQ_CASCADE]	= DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
	[DEC_IRQ_AB_RECV]	= -1,
	[DEC_IRQ_AB_XMIT]	= -1,
	[DEC_IRQ_DZ11]		= -1,
	[DEC_IRQ_ASC]		= IO_IRQ_NR(KN02BA_IO_INR_ASC),
	[DEC_IRQ_FLOPPY]	= -1,
	[DEC_IRQ_FPU]		= DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
	[DEC_IRQ_HALT]		= DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
	[DEC_IRQ_ISDN]		= -1,
	[DEC_IRQ_LANCE]		= IO_IRQ_NR(KN02BA_IO_INR_LANCE),
	[DEC_IRQ_MEMORY]	= IO_IRQ_NR(KN02BA_IO_INR_MEMORY),
	[DEC_IRQ_PSU]		= IO_IRQ_NR(KN02BA_IO_INR_PSU),
	[DEC_IRQ_RTC]		= IO_IRQ_NR(KN02BA_IO_INR_RTC),
	[DEC_IRQ_SCC0]		= IO_IRQ_NR(KN02BA_IO_INR_SCC0),
	[DEC_IRQ_SCC1]		= IO_IRQ_NR(KN02BA_IO_INR_SCC1),
	[DEC_IRQ_SII]		= -1,
	[DEC_IRQ_TC0]		= DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
	[DEC_IRQ_TC1]		= DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
	[DEC_IRQ_TC2]		= DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
	[DEC_IRQ_TIMER]		= -1,
	[DEC_IRQ_VIDEO]		= -1,
	[DEC_IRQ_ASC_MERR]	= IO_IRQ_NR(IO_INR_LANCE_MERR),
	[DEC_IRQ_ASC_ERR]	= IO_IRQ_NR(IO_INR_ASC_ERR),
	[DEC_IRQ_ASC_DMA]	= IO_IRQ_NR(IO_INR_ASC_DMA),
	[DEC_IRQ_FLOPPY_ERR]	= -1,
	[DEC_IRQ_ISDN_ERR]	= -1,
	[DEC_IRQ_ISDN_RXDMA]	= -1,
	[DEC_IRQ_ISDN_TXDMA]	= -1,
	[DEC_IRQ_LANCE_MERR]	= IO_IRQ_NR(IO_INR_LANCE_MERR),
	[DEC_IRQ_SCC0A_RXERR]	= IO_IRQ_NR(IO_INR_SCC0A_RXERR),
	[DEC_IRQ_SCC0A_RXDMA]	= IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
	[DEC_IRQ_SCC0A_TXERR]	= IO_IRQ_NR(IO_INR_SCC0A_TXERR),
	[DEC_IRQ_SCC0A_TXDMA]	= IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
	[DEC_IRQ_SCC0B_RXERR]	= -1,
	[DEC_IRQ_SCC0B_RXDMA]	= -1,
	[DEC_IRQ_SCC0B_TXERR]	= -1,
	[DEC_IRQ_SCC0B_TXDMA]	= -1,
	[DEC_IRQ_SCC1A_RXERR]	= IO_IRQ_NR(IO_INR_SCC1A_RXERR),
	[DEC_IRQ_SCC1A_RXDMA]	= IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
	[DEC_IRQ_SCC1A_TXERR]	= IO_IRQ_NR(IO_INR_SCC1A_TXERR),
	[DEC_IRQ_SCC1A_TXDMA]	= IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
};

static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
	{ { i: DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
		{ p: kn02xa_io_int } },
	{ { i: DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
		{ i: DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
	{ { i: DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
		{ i: DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
	{ { i: DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
		{ i: DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
	{ { i: DEC_CPU_IRQ_ALL },
		{ p: cpu_all_int } },
};

static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
	{ { i: IO_IRQ_MASK(KN02BA_IO_INR_MEMORY) },
		{ i: IO_IRQ_NR(KN02BA_IO_INR_MEMORY) } },
	{ { i: IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
		{ i: IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
	{ { i: IO_IRQ_DMA },
		{ p: asic_dma_int } },
	{ { i: IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
		{ i: IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
	{ { i: IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
		{ i: IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
	{ { i: IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
		{ i: IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
	{ { i: IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
		{ i: IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
	{ { i: IO_IRQ_ALL },
		{ p: asic_all_int } },
};

void __init dec_init_kn02ba(void)
{
	/* Setup some memory addresses. */
	ioasic_base = (void *) KN02BA_IOASIC_BASE;
	dec_rtc_base = (char *) KN02BA_RTC_BASE;

	/* IRQ routing. */
	memcpy(&dec_interrupt, &kn02ba_interrupt,
		sizeof(kn02ba_interrupt));

	/* CPU IRQ priorities. */
	memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
		sizeof(kn02ba_cpu_mask_nr_tbl));

	/* I/O ASIC IRQ priorities. */
	memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
		sizeof(kn02ba_asic_mask_nr_tbl));

	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
	init_ioasic_irqs(IO_IRQ_BASE);

}				/* dec_init_kn02ba */


/*
 * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
 * (xx = 20, 25, 33), aka MAXine.  Also applies to KN04(-CA), aka
 * DS5000/50, aka 4MAXine.
 */
static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
	[DEC_IRQ_CASCADE]	= DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
	[DEC_IRQ_AB_RECV]	= IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
	[DEC_IRQ_AB_XMIT]	= IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
	[DEC_IRQ_DZ11]		= -1,
	[DEC_IRQ_ASC]		= IO_IRQ_NR(KN02CA_IO_INR_ASC),
	[DEC_IRQ_FLOPPY]	= IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
	[DEC_IRQ_FPU]		= DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
	[DEC_IRQ_HALT]		= DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
	[DEC_IRQ_ISDN]		= IO_IRQ_NR(KN02CA_IO_INR_ISDN),
	[DEC_IRQ_LANCE]		= IO_IRQ_NR(KN02CA_IO_INR_LANCE),
	[DEC_IRQ_MEMORY]	= DEC_CPU_IRQ_NR(KN02CA_CPU_INR_MEMORY),
	[DEC_IRQ_PSU]		= -1,
	[DEC_IRQ_RTC]		= DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
	[DEC_IRQ_SCC0]		= IO_IRQ_NR(KN02CA_IO_INR_SCC0),
	[DEC_IRQ_SCC1]		= -1,
	[DEC_IRQ_SII]		= -1,
	[DEC_IRQ_TC0]		= IO_IRQ_NR(KN02CA_IO_INR_TC0),
	[DEC_IRQ_TC1]		= IO_IRQ_NR(KN02CA_IO_INR_TC1),
	[DEC_IRQ_TC2]		= -1,
	[DEC_IRQ_TIMER]		= DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
	[DEC_IRQ_VIDEO]		= IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
	[DEC_IRQ_ASC_MERR]	= IO_IRQ_NR(IO_INR_ASC_MERR),
	[DEC_IRQ_ASC_ERR]	= IO_IRQ_NR(IO_INR_ASC_ERR),
	[DEC_IRQ_ASC_DMA]	= IO_IRQ_NR(IO_INR_ASC_DMA),
	[DEC_IRQ_FLOPPY_ERR]	= IO_IRQ_NR(IO_INR_FLOPPY_ERR),
	[DEC_IRQ_ISDN_ERR]	= IO_IRQ_NR(IO_INR_ISDN_ERR),
	[DEC_IRQ_ISDN_RXDMA]	= IO_IRQ_NR(IO_INR_ISDN_RXDMA),
	[DEC_IRQ_ISDN_TXDMA]	= IO_IRQ_NR(IO_INR_ISDN_TXDMA),
	[DEC_IRQ_LANCE_MERR]	= IO_IRQ_NR(IO_INR_LANCE_MERR),
	[DEC_IRQ_SCC0A_RXERR]	= IO_IRQ_NR(IO_INR_SCC0A_RXERR),
	[DEC_IRQ_SCC0A_RXDMA]	= IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
	[DEC_IRQ_SCC0A_TXERR]	= IO_IRQ_NR(IO_INR_SCC0A_TXERR),
	[DEC_IRQ_SCC0A_TXDMA]	= IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
	[DEC_IRQ_SCC0B_RXERR]	= IO_IRQ_NR(IO_INR_SCC0B_RXERR),
	[DEC_IRQ_SCC0B_RXDMA]	= IO_IRQ_NR(IO_INR_SCC0B_RXDMA),
	[DEC_IRQ_SCC0B_TXERR]	= IO_IRQ_NR(IO_INR_SCC0B_TXERR),
	[DEC_IRQ_SCC0B_TXDMA]	= IO_IRQ_NR(IO_INR_SCC0B_TXDMA),
	[DEC_IRQ_SCC1A_RXERR]	= -1,
	[DEC_IRQ_SCC1A_RXDMA]	= -1,
	[DEC_IRQ_SCC1A_TXERR]	= -1,
	[DEC_IRQ_SCC1A_TXDMA]	= -1,
};

static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
	{ { i: DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_MEMORY) },
		{ i: DEC_CPU_IRQ_NR(KN02CA_CPU_INR_MEMORY) } },
	{ { i: DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
		{ i: DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
	{ { i: DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
		{ p: kn02xa_io_int } },
	{ { i: DEC_CPU_IRQ_ALL },
		{ p: cpu_all_int } },
};

static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
	{ { i: IO_IRQ_DMA },
		{ p: asic_dma_int } },
	{ { i: IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
		{ i: IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
	{ { i: IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
		{ i: IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
	{ { i: IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
		{ i: IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
	{ { i: IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
		{ i: IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
	{ { i: IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
		{ i: IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
	{ { i: IO_IRQ_ALL },
		{ p: asic_all_int } },
};

void __init dec_init_kn02ca(void)
{
	/* Setup some memory addresses. */
	ioasic_base = (void *) KN02CA_IOASIC_BASE;
	dec_rtc_base = (char *) KN02CA_RTC_BASE;

	/* IRQ routing. */
	memcpy(&dec_interrupt, &kn02ca_interrupt,
		sizeof(kn02ca_interrupt));

	/* CPU IRQ priorities. */
	memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
		sizeof(kn02ca_cpu_mask_nr_tbl));

	/* I/O ASIC IRQ priorities. */
	memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
		sizeof(kn02ca_asic_mask_nr_tbl));

	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
	init_ioasic_irqs(IO_IRQ_BASE);

}				/* dec_init_kn02ca */


/*
 * Machine-specific initialisation for KN03, aka DS5000/240,
 * aka 3max+ and DS5900, aka BIGmax.  Also applies to KN05, aka
 * DS5000/260, aka 4max+ and DS5900-260.
 */
static int kn03_interrupt[DEC_NR_INTS] __initdata = {
	[DEC_IRQ_CASCADE]	= DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
	[DEC_IRQ_AB_RECV]	= -1,
	[DEC_IRQ_AB_XMIT]	= -1,
	[DEC_IRQ_DZ11]		= -1,
	[DEC_IRQ_ASC]		= IO_IRQ_NR(KN03_IO_INR_ASC),
	[DEC_IRQ_FLOPPY]	= -1,
	[DEC_IRQ_FPU]		= DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
	[DEC_IRQ_HALT]		= DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
	[DEC_IRQ_ISDN]		= -1,
	[DEC_IRQ_LANCE]		= IO_IRQ_NR(KN03_IO_INR_LANCE),
	[DEC_IRQ_MEMORY]	= DEC_CPU_IRQ_NR(KN03_CPU_INR_MEMORY),
	[DEC_IRQ_PSU]		= IO_IRQ_NR(KN03_IO_INR_PSU),
	[DEC_IRQ_RTC]		= DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
	[DEC_IRQ_SCC0]		= IO_IRQ_NR(KN03_IO_INR_SCC0),
	[DEC_IRQ_SCC1]		= IO_IRQ_NR(KN03_IO_INR_SCC1),
	[DEC_IRQ_SII]		= -1,
	[DEC_IRQ_TC0]		= IO_IRQ_NR(KN03_IO_INR_TC0),
	[DEC_IRQ_TC1]		= IO_IRQ_NR(KN03_IO_INR_TC1),
	[DEC_IRQ_TC2]		= IO_IRQ_NR(KN03_IO_INR_TC2),
	[DEC_IRQ_TIMER]		= -1,
	[DEC_IRQ_VIDEO]		= -1,
	[DEC_IRQ_ASC_MERR]	= IO_IRQ_NR(IO_INR_ASC_MERR),
	[DEC_IRQ_ASC_ERR]	= IO_IRQ_NR(IO_INR_ASC_ERR),
	[DEC_IRQ_ASC_DMA]	= IO_IRQ_NR(IO_INR_ASC_DMA),
	[DEC_IRQ_FLOPPY_ERR]	= -1,
	[DEC_IRQ_ISDN_ERR]	= -1,
	[DEC_IRQ_ISDN_RXDMA]	= -1,
	[DEC_IRQ_ISDN_TXDMA]	= -1,
	[DEC_IRQ_LANCE_MERR]	= IO_IRQ_NR(IO_INR_LANCE_MERR),
	[DEC_IRQ_SCC0A_RXERR]	= IO_IRQ_NR(IO_INR_SCC0A_RXERR),
	[DEC_IRQ_SCC0A_RXDMA]	= IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
	[DEC_IRQ_SCC0A_TXERR]	= IO_IRQ_NR(IO_INR_SCC0A_TXERR),
	[DEC_IRQ_SCC0A_TXDMA]	= IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
	[DEC_IRQ_SCC0B_RXERR]	= -1,
	[DEC_IRQ_SCC0B_RXDMA]	= -1,
	[DEC_IRQ_SCC0B_TXERR]	= -1,
	[DEC_IRQ_SCC0B_TXDMA]	= -1,
	[DEC_IRQ_SCC1A_RXERR]	= IO_IRQ_NR(IO_INR_SCC1A_RXERR),
	[DEC_IRQ_SCC1A_RXDMA]	= IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
	[DEC_IRQ_SCC1A_TXERR]	= IO_IRQ_NR(IO_INR_SCC1A_TXERR),
	[DEC_IRQ_SCC1A_TXDMA]	= IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
};

static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
	{ { i: DEC_CPU_IRQ_MASK(KN03_CPU_INR_MEMORY) },
		{ i: DEC_CPU_IRQ_NR(KN03_CPU_INR_MEMORY) } },
	{ { i: DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
		{ i: DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
	{ { i: DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) }, 
		{ p: kn03_io_int } },
	{ { i: DEC_CPU_IRQ_ALL }, 
		{ p: cpu_all_int } },
};

static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
	{ { i: IO_IRQ_DMA },
		{ p: asic_dma_int } },
	{ { i: IO_IRQ_MASK(KN03_IO_INR_SCC0) },
		{ i: IO_IRQ_NR(KN03_IO_INR_SCC0) } },
	{ { i: IO_IRQ_MASK(KN03_IO_INR_SCC1) },
		{ i: IO_IRQ_NR(KN03_IO_INR_SCC1) } },
	{ { i: IO_IRQ_MASK(KN03_IO_INR_ASC) },
		{ i: IO_IRQ_NR(KN03_IO_INR_ASC) } },
	{ { i: IO_IRQ_MASK(KN03_IO_INR_LANCE) },
		{ i: IO_IRQ_NR(KN03_IO_INR_LANCE) } },
	{ { i: IO_IRQ_MASK(KN03_IO_INR_TC2) },
		{ i: IO_IRQ_NR(KN03_IO_INR_TC2) } },
	{ { i: IO_IRQ_MASK(KN03_IO_INR_TC1) },
		{ i: IO_IRQ_NR(KN03_IO_INR_TC1) } },
	{ { i: IO_IRQ_MASK(KN03_IO_INR_TC0) },
		{ i: IO_IRQ_NR(KN03_IO_INR_TC0) } },
	{ { i: IO_IRQ_ALL },
		{ p: asic_all_int } },
};

void __init dec_init_kn03(void)
{
	/* Setup some memory addresses.  */
	ioasic_base = (void *) KN03_IOASIC_BASE;
	dec_rtc_base = (char *) KN03_RTC_BASE;

	/* IRQ routing. */
	memcpy(&dec_interrupt, &kn03_interrupt,
		sizeof(kn03_interrupt));	

	/* CPU IRQ priorities. */
	memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
		sizeof(kn03_cpu_mask_nr_tbl));

	/* I/O ASIC IRQ priorities. */
	memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
		sizeof(kn03_asic_mask_nr_tbl));

	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
	init_ioasic_irqs(IO_IRQ_BASE);

}				/* dec_init_kn03 */


void __init init_IRQ(void)
{
	switch (mips_machtype) {
	case MACH_DS23100:	/* DS2100/DS3100 Pmin/Pmax */
		dec_init_kn01();
		break;
	case MACH_DS5100:	/* DS5100 MIPSmate */
		dec_init_kn230();
		break;
	case MACH_DS5000_200:	/* DS5000/200 3max */
		dec_init_kn02();
		break;
	case MACH_DS5000_1XX:	/* DS5000/1xx 3min */
		dec_init_kn02ba();
		break;
	case MACH_DS5000_2X0:	/* DS5000/240 3max+ */
		dec_init_kn03();
		break;
	case MACH_DS5000_XX:	/* Personal DS5000/xx */
		dec_init_kn02ca();
		break;
	case MACH_DS5800:	/* DS5800 Isis */
		panic("Don't know how to set this up!");
		break;
	case MACH_DS5400:	/* DS5400 MIPSfair */
		panic("Don't know how to set this up!");
		break;
	case MACH_DS5500:	/* DS5500 MIPSfair-2 */
		panic("Don't know how to set this up!");
		break;
	}
	set_except_vector(0, decstation_handle_int);

	/* Free the FPU interrupt if the exception is present. */
	if (!(mips_cpu.options & MIPS_CPU_NOFPUEX)) {
		cpu_fpu_mask = 0;
		dec_interrupt[DEC_IRQ_FPU] = -1;
	}

	/* Register board interrupts: FPU and cascade. */
	if (dec_interrupt[DEC_IRQ_FPU] >= 0)
		setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq);
	if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
		setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);

	/* Register the HALT interrupt. */
	if (dec_interrupt[DEC_IRQ_HALT] >= 0)
		setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
}

EXPORT_SYMBOL(dec_interrupt);