setup.c

microwindows移植到S3C44B0的源码

/*
 * Setup the interrupt stuff.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1998 Harald Koerfgen
 * Copyright (C) 2000, 2001, 2002  Maciej W. Rozycki
 */
#include <linux/config.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/param.h>
#include <linux/console.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>

#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/reboot.h>
#include <asm/traps.h>

#include <asm/dec/interrupts.h>
#include <asm/dec/kn01.h>
#include <asm/dec/kn02.h>
#include <asm/dec/kn02ba.h>
#include <asm/dec/kn02ca.h>
#include <asm/dec/kn03.h>
#include <asm/dec/kn230.h>
#include <asm/dec/ioasic.h>
#include <asm/dec/ioasic_addrs.h>
#include <asm/dec/ioasic_ints.h>


extern void dec_machine_restart(char *command);
extern void dec_machine_halt(void);
extern void dec_machine_power_off(void);
extern void dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);

extern asmlinkage void decstation_handle_int(void);


char *dec_rtc_base = (void *) KN01_RTC_BASE; /* Assume DS2100/3100 initially */

volatile u32 *ioasic_base;

/*
 * IRQ routing and priority tables.  Priorites are set as follows:
 *
 * 		KN01	KN230	KN02	KN02-BA	KN02-CA	KN03
 *
 * MEMORY	CPU	CPU	CPU	ASIC	CPU	CPU
 * RTC		CPU	CPU	CPU	ASIC	CPU	CPU
 * DMA		-	-	-	ASIC	ASIC	ASIC
 * SERIAL0	CPU	CPU	CSR	ASIC	ASIC	ASIC
 * SERIAL1	-	-	-	ASIC	-	ASIC
 * SCSI		CPU	CPU	CSR	ASIC	ASIC	ASIC
 * ETHERNET	CPU	*	CSR	ASIC	ASIC	ASIC
 * other	-	-	-	ASIC	-	-
 * TC2		-	-	CSR	CPU	ASIC	ASIC
 * TC1		-	-	CSR	CPU	ASIC	ASIC
 * TC0		-	-	CSR	CPU	ASIC	ASIC
 * other	-	CPU	-	CPU	ASIC	ASIC
 * other	-	-	-	-	CPU	CPU
 *
 * * -- shared with SCSI
 */
 
int dec_interrupt[DEC_NR_INTS] = {
	[0 ... DEC_NR_INTS - 1] = -1
};
int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
	{ { i: ~0 }, { p: dec_intr_unimplemented } },
};
int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
	{ { i: ~0 }, { p: asic_intr_unimplemented } },
};
int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);

static struct irqaction ioirq = {NULL, 0, 0, "cascade", NULL, NULL};
static struct irqaction fpuirq = {NULL, 0, 0, "fpu", NULL, NULL};

static struct irqaction haltirq = {dec_intr_halt, 0, 0, "halt", NULL, NULL};


extern void wbflush_setup(void);

extern struct rtc_ops dec_rtc_ops;

void (*board_time_init) (struct irqaction * irq);


/*
 * enable the periodic interrupts
 */
static void __init dec_time_init(struct irqaction *irq)
{
	/*
	* Here we go, enable periodic rtc interrupts.
	*/

#ifndef LOG_2_HZ
#  define LOG_2_HZ 7
#endif

	CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - LOG_2_HZ), RTC_REG_A);
	CMOS_WRITE(CMOS_READ(RTC_REG_B) | RTC_PIE, RTC_REG_B);
	setup_irq(dec_interrupt[DEC_IRQ_RTC], irq);
}


/*
 * Bus error (DBE/IBE exceptions and memory interrupts) handling
 * setup.  Nothing for now.
 */
void __init bus_error_init(void)
{
}


void __init decstation_setup(void)
{
	board_time_init = dec_time_init;

	wbflush_setup();

	_machine_restart = dec_machine_restart;
	_machine_halt = dec_machine_halt;
	_machine_power_off = dec_machine_power_off;

#ifdef CONFIG_FB
	conswitchp = &dummy_con;
#endif

	rtc_ops = &dec_rtc_ops;
}


/*
 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
 * or DS3100 (aka Pmax).
 */
static int kn01_interrupt[DEC_NR_INTS] __initdata = {
	[DEC_IRQ_CASCADE]	= -1,
	[DEC_IRQ_AB_RECV]	= -1,
	[DEC_IRQ_AB_XMIT]	= -1,
	[DEC_IRQ_DZ11]		= DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
	[DEC_IRQ_ASC]		= -1,
	[DEC_IRQ_FLOPPY]	= -1,
	[DEC_IRQ_FPU]		= DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
	[DEC_IRQ_HALT]		= -1,
	[DEC_IRQ_ISDN]		= -1,
	[DEC_IRQ_LANCE]		= DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
	[DEC_IRQ_MEMORY]	= DEC_CPU_IRQ_NR(KN01_CPU_INR_MEMORY),
	[DEC_IRQ_PSU]		= -1,
	[DEC_IRQ_RTC]		= DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
	[DEC_IRQ_SCC0]		= -1,
	[DEC_IRQ_SCC1]		= -1,
	[DEC_IRQ_SII]		= DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
	[DEC_IRQ_TC0]		= -1,
	[DEC_IRQ_TC1]		= -1,
	[DEC_IRQ_TC2]		= -1,
	[DEC_IRQ_TIMER]		= -1,
	[DEC_IRQ_VIDEO]		= DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
	[DEC_IRQ_ASC_MERR]	= -1,
	[DEC_IRQ_ASC_ERR]	= -1,
	[DEC_IRQ_ASC_DMA]	= -1,
	[DEC_IRQ_FLOPPY_ERR]	= -1,
	[DEC_IRQ_ISDN_ERR]	= -1,
	[DEC_IRQ_ISDN_RXDMA]	= -1,
	[DEC_IRQ_ISDN_TXDMA]	= -1,
	[DEC_IRQ_LANCE_MERR]	= -1,
	[DEC_IRQ_SCC0A_RXERR]	= -1,
	[DEC_IRQ_SCC0A_RXDMA]	= -1,
	[DEC_IRQ_SCC0A_TXERR]	= -1,
	[DEC_IRQ_SCC0A_TXDMA]	= -1,
	[DEC_IRQ_SCC0B_RXERR]	= -1,
	[DEC_IRQ_SCC0B_RXDMA]	= -1,
	[DEC_IRQ_SCC0B_TXERR]	= -1,
	[DEC_IRQ_SCC0B_TXDMA]	= -1,
	[DEC_IRQ_SCC1A_RXERR]	= -1,
	[DEC_IRQ_SCC1A_RXDMA]	= -1,
	[DEC_IRQ_SCC1A_TXERR]	= -1,
	[DEC_IRQ_SCC1A_TXDMA]	= -1,
};

static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
	{ { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_MEMORY) },
		{ i: DEC_CPU_IRQ_NR(KN01_CPU_INR_MEMORY) } },
	{ { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
		{ i: DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
	{ { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
		{ i: DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
	{ { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
		{ i: DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
	{ { i: DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
		{ i: DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
	{ { i: DEC_CPU_IRQ_ALL },
		{ p: cpu_all_int } },
};

void __init dec_init_kn01(void)
{
	/* Setup some memory addresses. */
	dec_rtc_base = (char *) KN01_RTC_BASE;

	/* IRQ routing. */
	memcpy(&dec_interrupt, &kn01_interrupt,
		sizeof(kn01_interrupt));

	/* CPU IRQ priorities. */
	memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
		sizeof(kn01_cpu_mask_nr_tbl));

	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);

}				/* dec_init_kn01 */


/*
 * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
 */
static int kn230_interrupt[DEC_NR_INTS] __initdata = {
	[DEC_IRQ_CASCADE]	= -1,
	[DEC_IRQ_AB_RECV]	= -1,
	[DEC_IRQ_AB_XMIT]	= -1,
	[DEC_IRQ_DZ11]		= DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
	[DEC_IRQ_ASC]		= -1,
	[DEC_IRQ_FLOPPY]	= -1,
	[DEC_IRQ_FPU]		= DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
	[DEC_IRQ_HALT]		= DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
	[DEC_IRQ_ISDN]		= -1,
	[DEC_IRQ_LANCE]		= DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
	[DEC_IRQ_MEMORY]	= DEC_CPU_IRQ_NR(KN230_CPU_INR_MEMORY),
	[DEC_IRQ_PSU]		= -1,
	[DEC_IRQ_RTC]		= DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
	[DEC_IRQ_SCC0]		= -1,
	[DEC_IRQ_SCC1]		= -1,
	[DEC_IRQ_SII]		= DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
	[DEC_IRQ_TC0]		= -1,
	[DEC_IRQ_TC1]		= -1,
	[DEC_IRQ_TC2]		= -1,
	[DEC_IRQ_TIMER]		= -1,
	[DEC_IRQ_VIDEO]		= -1,
	[DEC_IRQ_ASC_MERR]	= -1,
	[DEC_IRQ_ASC_ERR]	= -1,
	[DEC_IRQ_ASC_DMA]	= -1,
	[DEC_IRQ_FLOPPY_ERR]	= -1,
	[DEC_IRQ_ISDN_ERR]	= -1,
	[DEC_IRQ_ISDN_RXDMA]	= -1,
	[DEC_IRQ_ISDN_TXDMA]	= -1,
	[DEC_IRQ_LANCE_MERR]	= -1,
	[DEC_IRQ_SCC0A_RXERR]	= -1,
	[DEC_IRQ_SCC0A_RXDMA]	= -1,
	[DEC_IRQ_SCC0A_TXERR]	= -1,
	[DEC_IRQ_SCC0A_TXDMA]	= -1,
	[DEC_IRQ_SCC0B_RXERR]	= -1,
	[DEC_IRQ_SCC0B_RXDMA]	= -1,
	[DEC_IRQ_SCC0B_TXERR]	= -1,
	[DEC_IRQ_SCC0B_TXDMA]	= -1,
	[DEC_IRQ_SCC1A_RXERR]	= -1,
	[DEC_IRQ_SCC1A_RXDMA]	= -1,
	[DEC_IRQ_SCC1A_TXERR]	= -1,
	[DEC_IRQ_SCC1A_TXDMA]	= -1,
};

static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
	{ { i: DEC_CPU_IRQ_MASK(KN230_CPU_INR_MEMORY) },
		{ i: DEC_CPU_IRQ_NR(KN230_CPU_INR_MEMORY) } },
	{ { i: DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
		{ i: DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
	{ { i: DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
		{ i: DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
	{ { i: DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
		{ i: DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
	{ { i: DEC_CPU_IRQ_ALL },
		{ p: cpu_all_int } },
};

void __init dec_init_kn230(void)
{
	/* Setup some memory addresses. */
	dec_rtc_base = (char *) KN01_RTC_BASE;

	/* IRQ routing. */
	memcpy(&dec_interrupt, &kn230_interrupt,
		sizeof(kn230_interrupt));

	/* CPU IRQ priorities. */
	memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
		sizeof(kn230_cpu_mask_nr_tbl));

	mips_cpu_irq_init(DEC_CPU_IRQ_BASE);

}				/* dec_init_kn230 */


/*
 * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
 */
static int kn02_interrupt[DEC_NR_INTS] __initdata = {
	[DEC_IRQ_CASCADE]	= DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
	[DEC_IRQ_AB_RECV]	= -1,
	[DEC_IRQ_AB_XMIT]	= -1,
	[DEC_IRQ_DZ11]		= KN02_IRQ_NR(KN02_CSR_INR_DZ11),
	[DEC_IRQ_ASC]		= KN02_IRQ_NR(KN02_CSR_INR_ASC),
	[DEC_IRQ_FLOPPY]	= -1,
	[DEC_IRQ_FPU]		= DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
	[DEC_IRQ_HALT]		= -1,
	[DEC_IRQ_ISDN]		= -1,
	[DEC_IRQ_LANCE]		= KN02_IRQ_NR(KN02_CSR_INR_LANCE),
	[DEC_IRQ_MEMORY]	= DEC_CPU_IRQ_NR(KN02_CPU_INR_MEMORY),
	[DEC_IRQ_PSU]		= -1,
	[DEC_IRQ_RTC]		= DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
	[DEC_IRQ_SCC0]		= -1,
	[DEC_IRQ_SCC1]		= -1,
	[DEC_IRQ_SII]		= -1,
	[DEC_IRQ_TC0]		= KN02_IRQ_NR(KN02_CSR_INR_TC0),
	[DEC_IRQ_TC1]		= KN02_IRQ_NR(KN02_CSR_INR_TC1),
	[DEC_IRQ_TC2]		= KN02_IRQ_NR(KN02_CSR_INR_TC2),
	[DEC_IRQ_TIMER]		= -1,
	[DEC_IRQ_VIDEO]		= -1,
	[DEC_IRQ_ASC_MERR]	= -1,
	[DEC_IRQ_ASC_ERR]	= -1,
	[DEC_IRQ_ASC_DMA]	= -1,
	[DEC_IRQ_FLOPPY_ERR]	= -1,
	[DEC_IRQ_ISDN_ERR]	= -1,
	[DEC_IRQ_ISDN_RXDMA]	= -1,
	[DEC_IRQ_ISDN_TXDMA]	= -1,
	[DEC_IRQ_LANCE_MERR]	= -1,
	[DEC_IRQ_SCC0A_RXERR]	= -1,
	[DEC_IRQ_SCC0A_RXDMA]	= -1,
	[DEC_IRQ_SCC0A_TXERR]	= -1,
	[DEC_IRQ_SCC0A_TXDMA]	= -1,
	[DEC_IRQ_SCC0B_RXERR]	= -1,
	[DEC_IRQ_SCC0B_RXDMA]	= -1,
	[DEC_IRQ_SCC0B_TXERR]	= -1,
	[DEC_IRQ_SCC0B_TXDMA]	= -1,
	[DEC_IRQ_SCC1A_RXERR]	= -1,
	[DEC_IRQ_SCC1A_RXDMA]	= -1,
	[DEC_IRQ_SCC1A_TXERR]	= -1,
	[DEC_IRQ_SCC1A_TXDMA]	= -1,
};

static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
	{ { i: DEC_CPU_IRQ_MASK(KN02_CPU_INR_MEMORY) },
		{ i: DEC_CPU_IRQ_NR(KN02_CPU_INR_MEMORY) } },
	{ { i: DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
		{ i: DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
	{ { i: DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
		{ p: kn02_io_int } },
	{ { i: DEC_CPU_IRQ_ALL },
		{ p: cpu_all_int } },
};

static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
	{ { i: KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
		{ i: KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
	{ { i: KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
		{ i: KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
	{ { i: KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
		{ i: KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
	{ { i: KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
		{ i: KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
	{ { i: KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
		{ i: KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
	{ { i: KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
		{ i: KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
	{ { i: KN02_IRQ_ALL },
		{ p: kn02_all_int } },
};

void __init dec_init_kn02(void)
{
	/* Setup some memory addresses. */
	dec_rtc_base = (char *) KN02_RTC_BASE;