flashdrv.c

microwindows移植到S3C44B0的源码

{
	unsigned char c, rc;
	unsigned short s, rs;
	register unsigned int rw;
	register unsigned int regValue;
	register unsigned int FirstAddr, SecondAddr, ThirdAddr;
	register unsigned int FirstData, SecondData, ThirdData;
	register unsigned int data10, data20, data70, data80;

	if ((flashTypes[POINTER_TO_FLASH] == AMD_FLASH) || \
	    (flashTypes[POINTER_TO_FLASH] == ST_FLASH)) {
		switch (FLASH_WIDTH) {
		case 1:	/* Split the 32 bit write into four 8bit Writings */
			if (FLASH_MODE == PURE8) {	/* Boot Flash */
				FirstAddr = 0x5555;
				SecondAddr = 0x2aaa;
				ThirdAddr = 0x5555;
			} else {
				FirstAddr = 0xaaaa;
				SecondAddr = 0x5555;
				ThirdAddr = 0xaaaa;
			}
			WRITE_CHAR(FLASH_BASE_ADDRESS + FirstAddr, 0xaa);
			WRITE_CHAR(FLASH_BASE_ADDRESS + SecondAddr, 0x55);
			WRITE_CHAR(FLASH_BASE_ADDRESS + ThirdAddr, 0xa0);
#ifdef BE
			c = (data >> 24);
#else
			c = data;
#endif
			WRITE_CHAR(FLASH_BASE_ADDRESS + offset, c);
			/* Writing first Byte */
			while (true) {
				READ_CHAR(FLASH_BASE_ADDRESS + offset,
					  &rc);
				if ((rc & 0x80) == (c & 0x80))	/* DQ7 =? DATA */
					break;	/* DQ7 =  DATA */
				if ((rc & 0x20) == 0x20) {	/* DQ5 =? '1'  */
					READ_CHAR(FLASH_BASE_ADDRESS +
						  offset, &rc);
					if ((rc & 0x80) == (c & 0x80))
						break;	/* DQ7 = DATA  */
					else
						return false;	/* DQ7 != DATA */
				}
			}
			WRITE_CHAR(FLASH_BASE_ADDRESS + FirstAddr, 0xaa);
			WRITE_CHAR(FLASH_BASE_ADDRESS + SecondAddr, 0x55);
			WRITE_CHAR(FLASH_BASE_ADDRESS + ThirdAddr, 0xa0);
#ifdef BE
			c = (data >> 16);
#else
			c = (data >> 8);
#endif
			WRITE_CHAR(FLASH_BASE_ADDRESS + offset + 1, c);
			/* Writing second Byte */
			while (true) {
				READ_CHAR(FLASH_BASE_ADDRESS + offset + 1,
					  &rc);
				if ((rc & 0x80) == (c & 0x80))	/* DQ7 =? DATA */
					break;	/* DQ7 = DATA  */
				if ((rc & 0x20) == 0x20) {	/* DQ5 =? '1'  */
					READ_CHAR(FLASH_BASE_ADDRESS +
						  offset + 1, &rc);
					if ((rc & 0x80) == (c & 0x80))
						break;	/* DQ7 = DATA  */
					else
						return false;	/* DQ7 != DATA */
				}
			}
			WRITE_CHAR(FLASH_BASE_ADDRESS + FirstAddr, 0xaa);
			WRITE_CHAR(FLASH_BASE_ADDRESS + SecondAddr, 0x55);
			WRITE_CHAR(FLASH_BASE_ADDRESS + ThirdAddr, 0xa0);
#ifdef BE
			c = (data >> 8);
#else
			c = (data >> 16);
#endif
			WRITE_CHAR(FLASH_BASE_ADDRESS + offset + 2, c);
			/* Writing third Byte */
			while (true) {
				READ_CHAR(FLASH_BASE_ADDRESS + offset + 2,
					  &rc);
				if ((rc & 0x80) == (c & 0x80))	/* DQ7 =? DATA */
					break;	/* DQ7 = DATA  */
				if ((rc & 0x20) == 0x20) {	/* DQ5 =? '1'  */
					READ_CHAR(FLASH_BASE_ADDRESS +
						  offset + 2, &rc);
					if ((rc & 0x80) == (c & 0x80))
						break;	/* DQ7 = DATA  */
					else
						return false;	/* DQ7 != DATA */
				}
			}
			WRITE_CHAR(FLASH_BASE_ADDRESS + FirstAddr, 0xaa);
			WRITE_CHAR(FLASH_BASE_ADDRESS + SecondAddr, 0x55);
			WRITE_CHAR(FLASH_BASE_ADDRESS + ThirdAddr, 0xa0);
#ifdef BE
			c = data;
#else
			c = (data >> 24);
#endif
			WRITE_CHAR(FLASH_BASE_ADDRESS + offset + 3, c);
			/* Writing fourth Byte */
			while (true) {
				READ_CHAR(FLASH_BASE_ADDRESS + offset + 3,
					  &rc);
				if ((rc & 0x80) == (c & 0x80))	/* DQ7 =? DATA */
					break;	/* DQ7 = DATA  */
				if ((rc & 0x20) == 0x20) {	/* DQ5 =? '1'  */
					READ_CHAR(FLASH_BASE_ADDRESS +
						  offset + 3, &rc);
					if ((rc & 0x80) == (c & 0x80))
						break;	/* DQ7 = DATA  */
					else
						return false;	/* DQ7 != DATA */
				}
			}
			break;
		case 2:	/* Split the 32 bit write into two 8/16 bit Writings 
				   (16bit width). */
			if (FLASH_MODE == X16) {
				FirstData = 0xaa;	/* Data for the First  Cycle    */
				SecondData = 0x55;	/* Data for the Second Cycle    */
				ThirdData = 0xa0;	/* Data for the Third  Cycle    */
				FirstAddr = 0x5555;	/* Address for the First  Cycle */
				SecondAddr = 0x2aaa;	/* Address for the Second Cycle */
				ThirdAddr = 0x5555;	/* Address for the Third  Cycle */
			} else {	/* if (FLASH_MODE == 8) */

				FirstData = 0xaaaa;	/* Data for the First  Cycle    */
				SecondData = 0x5555;	/* Data for the Second Cycle    */
				ThirdData = 0xa0a0;	/* Data for the Third  Cycle    */
				FirstAddr = 0xaaaa;	/* Address for the First  Cycle */
				SecondAddr = 0x5555;	/* Address for the Second Cycle */
				ThirdAddr = 0xaaaa;	/* Address for the Third  Cycle */
			}
			WRITE_SHORT(FLASH_BASE_ADDRESS +
				    FirstAddr * FLASH_WIDTH, FirstData);
			WRITE_SHORT(FLASH_BASE_ADDRESS +
				    SecondAddr * FLASH_WIDTH, SecondData);
			WRITE_SHORT(FLASH_BASE_ADDRESS +
				    ThirdAddr * FLASH_WIDTH, ThirdData);
#ifdef BE
			s = (data >> 16);
#else
			s = data;
#endif
			WRITE_SHORT(FLASH_BASE_ADDRESS + offset, s);
			/* Writing Two Bytes */
			if (FLASH_MODE == X16) {
				data80 = 0x80;;
				data20 = 0x20;;
			} else {	/* if (FLASH_MODE == 8) */

				data80 = 0x8080;
				data20 = 0x2020;
			}
			while (true) {
				READ_SHORT(FLASH_BASE_ADDRESS + offset,
					   &rs);
				if ((rs & data80) == (s & data80))	/* DQ7 =? DATA */
					break;	/* DQ7 =  DATA */
				if ((rs & data20) == data20) {	/* DQ5 =? DATA */
					READ_SHORT(FLASH_BASE_ADDRESS +
						   offset, &rs);
					if ((rs & data80) == (s & data80))
						break;	/* DQ7 = DATA  */
					else {
						flashReset();
						return false;	/* DQ7 != DATA */
					}
				}
			}
			WRITE_SHORT(FLASH_BASE_ADDRESS +
				    FirstAddr * FLASH_WIDTH, FirstData);
			WRITE_SHORT(FLASH_BASE_ADDRESS +
				    SecondAddr * FLASH_WIDTH, SecondData);
			WRITE_SHORT(FLASH_BASE_ADDRESS +
				    ThirdAddr * FLASH_WIDTH, ThirdData);
#ifdef BE
			s = data;
#else
			s = (data >> 16);
#endif
			WRITE_SHORT(FLASH_BASE_ADDRESS + offset + 2, s);
			/* Writing Two Bytes */
			while (true) {
				READ_SHORT(FLASH_BASE_ADDRESS + offset + 2,
					   &rs);
				if ((rs & data80) == (s & data80))	/* DQ7 =? DATA */
					break;	/* DQ7 =  DATA */
				if ((rs & data20) == data20) {	/* DQ5 =? '1'  */
					READ_SHORT(FLASH_BASE_ADDRESS +
						   offset + 2, &rs);
					if ((rs & data80) == (s & data80))
						break;	/* DQ7 = DATA  */
					else {
						flashReset();
						return false;	/* DQ7 != DATA */
					}
				}
			}
			return true;
		case 4:
		case 8:
			if (FLASH_MODE == X16) {
				FirstData = 0x00aa00aa;
				SecondData = 0x00550055;
				ThirdData = 0x00a000a0;
				FirstAddr = 0x5555;
				SecondAddr = 0x2aaa;
				ThirdAddr = 0x5555;
			} else {	/* (FLASH_MODE == 8) */

				FirstData = 0xaaaaaaaa;	/* Data for the First  Cycle    */
				SecondData = 0x55555555;	/* Data for the Second Cycle    */
				ThirdData = 0xa0a0a0a0;	/* Data for the Third  Cycle    */
				FirstAddr = 0xaaaaaaaa;	/* Address for the First  Cycle */
				SecondAddr = 0x55555555;	/* Address for the Second Cycle */
				ThirdAddr = 0xaaaaaaaa;	/* Address for the Third  Cycle */
			}
			WRITE_WORD(FLASH_BASE_ADDRESS + FirstAddr *
				   FLASH_WIDTH + offset % FLASH_WIDTH,
				   FirstData);
			WRITE_WORD(FLASH_BASE_ADDRESS +
				   SecondAddr * FLASH_WIDTH +
				   offset % FLASH_WIDTH, SecondData);
			WRITE_WORD(FLASH_BASE_ADDRESS +
				   ThirdAddr * FLASH_WIDTH +
				   offset % FLASH_WIDTH, ThirdData);
			/* writting the word. */
			WRITE_WORD(FLASH_BASE_ADDRESS + offset, data);
			/* preparing the polling patterns. */
			if (FLASH_MODE == X16) {
				data80 = 0x00800080;
				data20 = 0x00200020;
			} else {	/* (FLASH_MODE == 8) */

				data80 = 0x80808080;
				data20 = 0x20202020;
			}
			while (true) {	/* polling loop. */
				rw = READWORD(FLASH_BASE_ADDRESS + offset);
				/* DQ7 =? DATA */
				if ((rw & data80) == (data & data80))
					break;	/* DQ7 =  DATA */
				if ((rw & data20) == data20) {	/* DQ5 =? '1'  */
					rw =
					    READWORD(FLASH_BASE_ADDRESS +
						     offset);
					if ((rw & data80) ==
					    (data & data80)) break;	/* DQ7 = DATA  */
					else
						return false;	/* DQ7 != DATA */
				}
			}
			return true;
		default:
			return false;	/* case of invalid flash Width. */
		}
	} else {		/* Intel/Micron */

		switch (FLASH_WIDTH) {
		case 1:
			/* Writing First Byte */
			WRITE_CHAR(FLASH_BASE_ADDRESS, 0x10);
#ifdef BE
			c = (data >> 24);
#else
			c = data;
#endif
			WRITE_CHAR(FLASH_BASE_ADDRESS + offset, c);
			while (true) {
				/* Reading STATUS Register */
				WRITE_CHAR(FLASH_BASE_ADDRESS, 0x70);
				regValue = READCHAR(FLASH_BASE_ADDRESS);
				if ((regValue & 0x80) == 0x80)
					break;	/* Case of Write-Operation had Ended */
			}
			/* Reading STATUS Register for Writing Verification */
			WRITE_CHAR(FLASH_BASE_ADDRESS, 0x70);
			regValue = READCHAR(FLASH_BASE_ADDRESS);
			if ((regValue & 0x10) == 0x10)
				return false;	/* Write failure */

			/* Writing Second Byte */
			WRITE_CHAR(FLASH_BASE_ADDRESS + 1, 0x10);
#ifdef BE
			c = (data >> 16);
#else
			c = (data >> 8);
#endif
			WRITE_CHAR(FLASH_BASE_ADDRESS + offset + 1, c);
			while (true) {
				/* Reading STATUS Register */
				WRITE_CHAR(FLASH_BASE_ADDRESS + 1, 0x70);
				regValue =
				    READCHAR(FLASH_BASE_ADDRESS + 1);
				if ((regValue & 0x80) == 0x80)
					break;	/* Write operation ended */
			}
			/* Reading STATUS Register for Writing verification */
			WRITE_CHAR(FLASH_BASE_ADDRESS + 1, 0x70);
			regValue = READCHAR(FLASH_BASE_ADDRESS + 1);
			if ((regValue & 0x10) == 0x10)
				return false;	/* Write failure */

			/* Writing Third Byte */
			WRITE_CHAR(FLASH_BASE_ADDRESS + 2, 0x10);
#ifdef BE
			c = (data >> 8);
#else
			c = (data >> 16);
#endif
			WRITE_CHAR(FLASH_BASE_ADDRESS + offset + 2, c);
			while (true) {
				/* Reading STATUS Register */
				WRITE_CHAR(FLASH_BASE_ADDRESS + 2, 0x70);
				regValue =
				    READCHAR(FLASH_BASE_ADDRESS + 2);
				if ((regValue & 0x80) == 0x80)
					break;	/* Write operation ended */
			}
			/* Reading STATUS Register for Writing Verification */
			WRITE_CHAR(FLASH_BASE_ADDRESS + 2, 0x70);
			regValue = READCHAR(FLASH_BASE_ADDRESS + 2);
			if ((regValue & 0x10) == 0x10)
				return false;	/* Write failure */

			/* Writing Fourth Byte */
			WRITE_CHAR(FLASH_BASE_ADDRESS + 3, 0x10);
#ifdef BE
			c = data;
#else
			c = (data >> 24);
#endif
			WRITE_CHAR(FLASH_BASE_ADDRESS + offset + 3, c);
			while (true) {
				/* Reading STATUS Register */
				WRITE_CHAR(FLASH_BASE_ADDRESS + 3, 0x70);
				regValue =
				    READCHAR(FLASH_BASE_ADDRESS + 3);
				if ((regValue & 0x80) == 0x80)
					break;	/* Write operation ended */
			}
			/* Reading STATUS Register for Writing Verification */
			WRITE_CHAR(FLASH_BASE_ADDRESS + 3, 0x70);
			regValue = READCHAR(FLASH_BASE_ADDRESS + 3);
			if ((regValue & 0x10) == 0x10)
				return false;	/* Write failure */
			flashReset();
			return true;
		case 2:
			if (FLASH_MODE == X16) {	/* Case of one X16 bit device */
				FirstData = 0x0010;	/* Data for the First  Cycle  */
			} else {	/* if (FLASH_MODE == 8) ==> Case of two X8 bit devices */

				FirstData = 0x1010;	/* Data for the First  Cycle  */
			}
			/* Writing First two Bytes */
			WRITE_SHORT(FLASH_BASE_ADDRESS, FirstData);
#ifdef BE
			s = (data >> 16);
#else
			s = data;
#endif
			WRITE_SHORT(FLASH_BASE_ADDRESS + offset, s);
			if (FLASH_MODE == X16) {
				data70 = 0x0070;
				data80 = 0x0080;
				data10 = 0x0010;
			} else {	/* case of (FLASH_MODE == X8) */

				data70 = 0x7070;
				data80 = 0x8080;
				data10 = 0x1010;
			}
			/* polling on writing action => when done break. */
			while (true) {
				WRITE_SHORT(FLASH_BASE_ADDRESS, data70);
				regValue = READSHORT(FLASH_BASE_ADDRESS);
				if ((regValue & data80) == data80)
					break;
			}
			/* Reading STATUS Register for Writing Verification */
			WRITE_CHAR(FLASH_BASE_ADDRESS, data70);
			regValue = READCHAR(FLASH_BASE_ADDRESS);
			if ((regValue & data10) == data10)
				return false;	/* Write failure */
			/* Writing Last two Bytes */