📄 bootloader.s
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; word in flash to copy
COPY_8_WORDS
ldmia r10!, {r0-r7} ;-Load 8 words from flash
stmia r9!, {r0-r7} ;-Store 8 words to SRAM0
cmp r10, r11 ;-Repeat until SRAM0 is
blo COPY_8_WORDS ; full
BRANCH_TO_SRAM0
ldr r0, =EXC_SPSRAM_BLOCK0_BASE ;-Branch to SRAM0 where
ldr r1, =EXC_EBI_BLOCK0_BASE ; boot code was copied
sub r0, r1, r0
sub pc, pc, r0
nop ;-NOP is not executed as
; pipeline is flushed
;***************************************************************************
; Check for New Image
;
; The last thing that the webserver application does after it has received a
; new image is write 0x0001 to address 0x3FFFFC. This checks that value and
; if the value is 0x0001 a branch is take to the base of EBI1 and the new
; image is started. To return back to this application, the new image must
; erase the last block of flash on EBI0
;***************************************************************************
EBI1_CHECK
ldr r0, =(EXC_EBI_BLOCK0_BASE + 0x3FFFFC)
ldr r3, =0x0001FFFF ;
ldr r1, [r0]
cmp r1, r3
beq BRANCH_TO_EBI1
;***************************************************************************
; Setup Stripe IO
;
; Much of the Embedded Stripe I/O is dual purpose, meaning if the Stripe
; does not need it, it can be used as regular PLD I/O. This section sets
; up the SDRAM and EBI pins for stripe use, and the UART and TRACE pins for
; PLD use.
;***************************************************************************
ldr r0, =(EXC_REGISTERS_BASE + 0x40) ;-Load register
ldr r1, =0x7 ; IOCR_SDRAM
str r1, [r0] ; Fast slew rate, LVTTL,
; Stripe use
ldr r0, =(EXC_REGISTERS_BASE + 0x44) ;-Load register
ldr r1, =0x2 ; IOCR_EBI
str r1, [r0] ; Slow slew rate, LVTTL,
; Stripe use
ldr r0, =(EXC_REGISTERS_BASE + 0x48) ;-Load register
ldr r1, =0x2 ; IOCR_UART
str r1, [r0] ; Fast slew rate, LVTTL,
; PLD use
ldr r0, =(EXC_REGISTERS_BASE + 0x4C) ;-Load register
ldr r1, =0x5 ; IOCR_TRACE
str r1, [r0] ; Fast slew rate, LVTTL,
; PLD use
;***************************************************************************
; Turn on Cache
;
; This section reads register 1 of the MMU, turns on the instruction cache
; enable and round robin bits, then writes it back. At the end of this
; section, the instruction cache is turned on and running in round-robin
; mode
;
;***************************************************************************
; CP# Cop1 Rd CRn CRm Cop2 ;-Operands of MCR inst.
mrc p15, 0, r0, c1, c0, 0 ;-Read register 1 of MMU
ldr r1, =0x1000 ;-ICache enable bit mask
ldr r2, =0x4000 ;-Round Robin bit mask
orr r0, r0, r1 ;-Set ICache enable bit
orr r0, r0, r2 ;-Set Round Robin bit
mcr p15, 0, r0, c1, c0, 0 ;-Write back register 1
;***************************************************************************
; Setup SDRAM Controller
;
; This section configures the SDRAM controller for SDR SDRAM.
; Specifically, the SDRAM controller is setup to interface with a Crucial
; CT16M72S4D75.9T 128MB DIMM. First we wait to assure that PLL2 has been
; locked for 100us. At this point we load the registers SDRAM_TIMING1,
; SDRAM_TIMING2, SDRAM_CONFIG, SDRAM_REFRESH, SDRAM_ADDR, and SDRAM_MODE0.
; These registers configure how the SDRAM controller will interface with
; the SDRAM devices. Descriptions of these registers can be found in the
; ARM-based Excalibur Hardware Reference Manual.
;
;***************************************************************************
;We must wait 100us after PLL2 is locked.
ldr r6, =(EXC_REGISTERS_BASE + 0x328) ;-Load address of AHB1-COUNT
ldr r9, =12500
bl WAIT_FUNCTION ;-Wait for 12500 AHB1 cycles
; (100us)
LOAD_SDRAM_REGS
ldr r0, =(EXC_REGISTERS_BASE + 0x400) ;-Load register
ldr r1, =0x4A92 ; SDRAM_TIMING1
str r1, [r0] ; RCD=2, RAS=5, RRD=2,
; RP=2, WR=2
ldr r0, =(EXC_REGISTERS_BASE + 0x404) ;-Load register
ldr r1, =0x7BB8 ; SDRAM_TIMING2
str r1, [r0] ; RC=7, CL=3, BL=8,
; RFC=7
ldr r0, =(EXC_REGISTERS_BASE + 0x408) ;-Load register
ldr r1, =0x0 ; SDRAM_CONFIG
str r1, [r0] ; Type=SDR
ldr r0, =(EXC_REGISTERS_BASE + 0x40C) ;-Load register
ldr r1, =0x5DC ; SDRAM_REFRESH
str r1, [r0] ; Refresh=15us
ldr r0, =(EXC_REGISTERS_BASE + 0x410) ;-Load register
ldr r1, =0xCA80 ; SDRAM_ADDR
str r1, [r0] ; ROW=12, COL=10
ldr r0, =(EXC_REGISTERS_BASE + 0x420) ;-Load register
ldr r1, =0x033 ; SDRAM_MODE0
str r1, [r0] ; CAS=3, sequential,
; burst length=8
;***************************************************************************
; Initialize SDRAM
;
; The SDRAM has now been configured so now the SDRAM device attached
; externally to the SDRAM controller must be initialized. However, the
; initialization process must complete within one refresh cycle. For this
; reason, we want the initialization code to run as fast as possible. To
; accomplish this, we lock the SDRAM initialization code into instruction
; cache. After the code is locked in cache, the following initialization
; commands are issued to prepare SDRAM for reading and writing:
;
; -- Enable SDRAM controller
; -- Issue Precharge command
; -- Wait 50 SDRAM cycles
; -- *Note that the 50 cycle delay is only neccessary for XA10
; -- XA4 and XA1 do not require a delay between SDRAM commands
; -- Additionally, the delays in this example are determined by
; -- the clock frequencies involved. If different clock frequencies
; -- are used, delays will have to be re-calculated.
; -- Issue Refresh command
; -- Wait 50 SDRAM cycles
; -- Issue 2nd Refresh command
; -- Wait 50 SDRAM cycles
; -- Issue Load Mode command to load SDRAM_MODE0 into SDRAM device.
; -- Wait 50 SDRAM cycles
;
; Following this sequence, the SDRAM will be ready for reading and writing.
;
;***************************************************************************
adr r1,CACHE_THIS_CODE_START ;-Load begin of SDRAM
; init code
adr r2,CACHE_THIS_CODE_END ;-Load end of SDRAM
; init code
adr r3,CACHE_THIS_CODE2_START ;-Load begin of SDRAM
; init wait function
adr r4,CACHE_THIS_CODE2_END ;-Load end of SDRAM
; init wait function
SDR_Load_Cache ;-Lock SDRAM init code
mcr p15,0,r1,c7,c13,1 ; into instruction cache
add r1,r1,#8
cmp r1,r2
ble SDR_Load_Cache
SDR_Load_Cache2 ;-Lock SDRAM wait
mcr p15,0,r3,c7,c13,1 ; function into
add r3,r3,#8 ; instruction cache
cmp r3,r4
ble SDR_Load_Cache2
INIT_SDRAM
;Load bit masks for register SDRAM_INIT
ldr r2, =0x8000 ;-Enable bit mask
ldr r3, =0xC000 ;-Precharge bit mask
ldr r4, =0x8800 ;-Refresh bit mask
ldr r5, =0xA000 ;-Load Mode bit mask
ldr r6, =(EXC_REGISTERS_BASE + 0x328) ;-Load address of AHB1-COUNT
CACHE_THIS_CODE_START
ldr r0, =(EXC_REGISTERS_BASE + 0x41C) ;-Enable SDRAM controller
ldr r1, [r0] ; by setting enable bit of
orr r1, r1, r2 ; SDRAM_INIT
str r1, [r0]
str r3, [r0] ;-Issue Precharge cmd
; by setting Precharge
; bit of SDRAM_INIT
ldr r9, =63
bl WAIT_FUNCTION ;-Wait for 63 AHB1 cycles
str r4, [r0] ;-Issue Refresh command
; by setting Refresh bit
; of SDRAM_INIT
ldr r9, =63
bl WAIT_FUNCTION ;-Wait for 63 AHB1 cycles
str r4, [r0] ;-Issue Refresh command
; by setting Refresh bit
; of SDRAM_INIT
ldr r9, =63
bl WAIT_FUNCTION ;-Wait for 63 AHB1 cycles
str r5, [r0] ;-Issue Load Mode cmd
; by setting Load Mode
; bit of SDRAM_INIT
ldr r9, =63
bl WAIT_FUNCTION ;-Wait for 63 AHB1 cycles
CACHE_THIS_CODE_END
;-SDRAM is now ready for
; reading and writing.
CONFIGURE_PLD
ldr r0, =(EXC_REGISTERS_BASE + 0x144) ;-Set config_clock period
ldr r1, =0x4 ; to 7.8125MHz with
str r1, [r0] ; CONFIG_CLOCK reg (AHB2/8)
ldr r0, =(EXC_REGISTERS_BASE + 0x140) ;-Check Lock bit of
ldr r1, [r0] ; CONFIG_CONTROL
and r2, r1, #0x1
cmp r2, #0x1
beq PLD_LOCKED
orr r2, r1, #0x2 ;-Set CO bit of
str r2, [r0] ; CONFIG_CONTROL
ldr r0,=sbi_data ;-SBI data starts at the end of
ldr r1, =(EXC_REGISTERS_BASE + 0x8) ;-Load address of IDCODE reg
ldr r2, [r1] ;-Load IDCODE from device
ldr r3, [r0, #4] ;-Load IDCODE from SBI file
cmp r2, r3 ;-Compare two IDCODE's
bne SBI_IDCODE_ERROR ;-Take error vector if two
; IDCODE's dont match
ldr r0,=sbi_data; ;-Now look at flash copy of SBI
ldmia r0,{r1-r4} ;-Load the first 4 words
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