bootloader.s

altera epxa1的例子程序

;***************************************************************************
;  
;  2002 Altera Corporation. All rights reserved.  Altera products are protected    
;  under numerous U.S. and foreign patents, maskwork rights, copyrights and other  
;  intellectual property laws. This reference design file, and your use thereof,   
;  is subject to and governed by the terms and conditions of the applicable        
;  Altera Reference Design License Agreement (found at www.altera.com).  By using  
;  this reference design file, you indicate your acceptance of such terms and      
;  conditions between you and Altera Corporation.  In the event that you do not    
;  agree with such terms and conditions, you may not use the reference design file 
;  and please promptly destroy any copies you have made. This reference design     
;  file being provided on an "as-is" basis and as an accommodation and therefore   
;  all warranties, representations or guarantees of any kind (whether express,     
;  implied or statutory) including, without limitation, warranties of              
;  merchantability, non-infringement, or fitness for a particular purpose, are     
;  specifically disclaimed.  By making this reference design file available, Altera 
;  expressly does not recommend, suggest or require that this reference design file 
;  be used in combination with any other product not provided by Altera.
;           
;***************************************************************************
;
;				Filename: bootloader.s
;
; This code is used for initial system bring up.  
; It performs the following functions:
;				      Read IDCODE
;				      Setup PLLs
;				      Setup Memory Map 
;				      Copy Code to SRAM
;		                      Setup Stripe IO
;	                              Turn on I-Cache
;	                              Setup SDRAM Controller
;	                              Initialize SDRAM
;	                              PLD Configuration
;
; Many of these functions are implemented with the native Altera bootloader.  Because
; the Altera bootloader is written with the assumption that the code will be running out 
; of EBI0 this code was used to replace the functionality of the Altera bootloader.  
;  Continue to elaborate ***************************
;       
;***************************************************************************

	GET stripe.s    		; Megawizard Generated Defines for Stripe Memory Map
	GET serial.s			; Register Map for Stripe Uart 
	
	IMPORT  Reset_Handler           ; In init.s
	
	

        AREA bootloader, CODE, READONLY
	
	ENTRY
	
	
	
;***************************************************************************
; 			   Vector Table
;***************************************************************************
        

        B START
        B Undefined_Handler
        B SWI_Handler
        B Prefetch_Handler
        B Abort_Handler
        NOP                             ; Reserved vector
        B IRQ_Handler
        B FIQ_Handler

START


;***************************************************************************
;                           Read IDCODE
;
;  This section reads the IDCODE register at address (base + 0x8) and 
;  compares it to the XA10 IDCODE, 0x090010DD.  An error vector is taken if 
;  they do not match.

;***************************************************************************

    ldr     r0, =(EXC_REGISTERS_BASE + 0x8)         ;-Load address of IDCODE
    ldr     r1, [r0]                                ;-Load value of IDCODE
    ldr     r2, =0x090010DD                         ;-IDCODE for EPXA10
    cmp     r1,r2                                   ;-Compare IDCODE's
    bne     ID_Error  				    ;-Take error vector if
                                                    ; they do not match


;***************************************************************************
;                            Setup PLLs
;
;  The PLL setup section configures PLL1 and PLL2 to run at 166MHz and 
;  75MHz, respectively.  CLK_OUT = ((CLK_REF * (M / N)) / K).  With a 
;  CLK_REF of 50MHz, the values of PLL1 will be set to N=1, M=13, K=2 to 
;  make its output 166MHz.  Similarly, PLL2 will be set to N=1, M=12, M=4.
;  Since we are using SDR SDRAM, PLL2 needs to be setup for twice our 
;  desired SDRAM frequency (See ARM-based Excalibur Hardware Reference 
;  Manual).  After the PLLs are setup, they are both started by writing
;  the recommended value to CTRL, and a logic 1 to the P bit of the 
;  registers CLK_PLL1_CTRL and CLK_PLL2_CTRL.  The bypass bits are cleared
;  for both PLLs, then we wait for them to lock.  The final step is to clear 
;  the "lock change" bits after the PLLs are locked.  Since this is an 
;  expected change in lock status (we just started the PLLs), we dont want 
;  to take the interrupt that these bits cause.
;
;***************************************************************************


;Load the M, N, and K counters for PLL1 and PLL2.

    ldr     r0, =(EXC_REGISTERS_BASE + 0x300)       ;-Load address of CLK_PLL1_NCNT
    ldr     r1, =0x40000                            ;-N=1
    str     r1, [r0]                                ;-Load CLK_PLL1_NCNT


    ldr     r0, =(EXC_REGISTERS_BASE + 0x304)       ;-Load address of CLK_PLL1_MCNT
    ldr     r1, =0x10706                            ;-M=13
    str     r1, [r0]                                ;-Load CLK_PLL1_MCNT


    ldr     r0, =(EXC_REGISTERS_BASE + 0x308)       ;-Load address of CLK_PLL1_KCNT
    ldr     r1, =0x20101                            ;-K=2
    str     r1, [r0]                                ;-Load CLK_PLL1_KCNT


    ldr     r0, =(EXC_REGISTERS_BASE + 0x310)       ;-Load address of CLK_PLL2_NCNT
    ldr     r1, =0x40000                            ;-N=1
    str     r1, [r0]                                ;-Load CLK_PLL2_NCNT

    ldr     r0, =(EXC_REGISTERS_BASE + 0x314)       ;-Load address of CLK_PLL2_MCNT  
    ldr     r1, =0x20606                            ;-M=12
    str     r1, [r0]                                ;-Load CLK_PLL2_MCNT

    ldr     r0, =(EXC_REGISTERS_BASE + 0x318)       ;-Load address of CLK_PLL2_KCNT 
    ldr     r1, =0x20202                            ;-K=4
    str     r1, [r0]                                ;-Load CLK_PLL2_KCNT


;Set CTRL field in PLL control registers and start the PLLs.  The value written to 
;CLK_PLLx_CTRL is dependent upon the frequencies involved.

    ldr     r0, =(EXC_REGISTERS_BASE + 0x30C)       ;-Load address of CLK_PLL1_CTRL
    ldr     r1, =0x01055
    str     r1, [r0]                                ;-Start PLL1

    ldr     r0, =(EXC_REGISTERS_BASE + 0x31C)       ;-Load address of CLK_PLL2_CTRL
    str     r1, [r0]                                ;-Start PLL2


;Clear both PLLs' bypass bits

    ldr     r0, =(EXC_REGISTERS_BASE + 0x320)       ;-Load address of CLK_DERIVE
    ldr     r1, =0x10                               ;-Write 0x10 to it
    str     r1, [r0]                                ;  to clear bits 12, 13


;Wait for PLLs to lock

    ldr     r0, =(EXC_REGISTERS_BASE + 0x324)       ;-Load address of CLK_STATUS
PLL_CHECK
    ldr     r1, [r0]                                ;-Load value of CLK_STATUS
    cmp     r1, #0x3F                               ;-Check low 7 bits are '1'
    bne     PLL_CHECK                               ;-Loop until they are


;Since the lock change bits just went high, we need to clear them to prevent
;a resulting interrupt.  r0 should still contain the address of CLK_STATUS.

    ldr     r1, =0xC                                ;-Write '1's to bits 2, 3
    str     r1, [r0]                                ;  of CLK_STATUS




;***************************************************************************
;                Setup Memory Map and Copy Code to SRAM
;
;  In this section, we prepare the system to run software code out of SRAM.  
;  Upon entering this section, the boot code running is running out of Flash 
;  memory on EBI0.  This section performs the following steps.
;
;  -- Maps EBI0, EBI1, PLD0, SRAM0(should be 0x0), SRAM1, SDRAM0 and SDRAM1 
;     to the locations configured in the megawizard.  
;  -- Turn off default boot mapping as we no longer need an alias of EBI0 
;     at address 0x0  
;  -- Copy code from Flash on EBI0 to SRAM0 
;  -- Branch to new copy of code residing in SRAM0
;
;  At the end of this section, code is running out of SRAM0.  
;  
;***************************************************************************

SETUP_MEM_MAP


MAP_EBI0
    ldr     r0, =(EXC_REGISTERS_BASE + 0xC0)      ;-Map EBI0
    ldr     r1, =(EXC_EBI_BLOCK0_BASE +0xA83)     ;  by loading register
    str     r1, [r0]                              ;  MMAP_EBI0

EBI_BLOCK0
    ldr     r0, =(EXC_REGISTERS_BASE + 0x390)     ;-Set options for EBI Block0
    ldr     r1, =0x010				  ;  Wait States = 8
    str     r1, [r0]                              ;  EBI_block0

MAP_EBI1
    ldr     r0, =(EXC_REGISTERS_BASE + 0xC4)      ;-Map EBI1
    ldr     r1, =(EXC_EBI_BLOCK1_BASE +0xA83)     ;  by loading register
    str     r1, [r0]                              ;  MMAP_EBI1
    
EBI_BLOCK1
    ldr     r0, =(EXC_REGISTERS_BASE + 0x394)     ;-Set options for EBI Block1
    ldr     r1, =0x010				  ;  Wait States = 8
    str     r1, [r0]                              ;  EBI_block1  
	
EBI_CR
    ldr     r0, =(EXC_REGISTERS_BASE + 0x380)     ;-Set Global options for EBI 
    ldr     r1, =0x08				  ;  by loading register
    str     r1, [r0]                              ;  EBI_CR
    




BRANCH_TO_EBI0
    ldr     r0, =EXC_EBI_BLOCK0_BASE                ;-Branch to where EBI0
    add     pc, pc, r0                              ;  was just mapped.
    nop                                             ;-NOP is not executed as
       						    ;  pipeline is flushed  
       						    ;  when pc is altered.    												
TURN_OFF_BOOT_MAP
    ldr     r0, =(EXC_REGISTERS_BASE + 0x0)         ;-Turn off boot mapping
    ldr     r1, =0x1                                ;  by loading register
    str     r1, [r0]                                ;  BOOT_CR 

MAP_SRAM0
    ldr     r0, =(EXC_REGISTERS_BASE + 0x90)        ;-Map SRAM0
    ldr     r1, =(EXC_SPSRAM_BLOCK0_BASE + 0x803)   ;  by loading register
    str     r1, [r0]                                ;  MMAP_SRAM0

MAP_SRAM1
    ldr     r0, =(EXC_REGISTERS_BASE + 0x94)        ;-Map SRAM1
    ldr     r1, =(EXC_SPSRAM_BLOCK1_BASE + 0x803)   ;  by loading register
    str     r1, [r0]                                ;  MMAP_SRAM1
    
MAP_SDRAM0
    ldr     r0, =(EXC_REGISTERS_BASE + 0xB0)        ;-Map SRAM0
    ldr     r1, =(EXC_SDRAM_BLOCK0_BASE + 0xC81)    ;  by loading register
    str     r1, [r0]                                ;  MMAP_SRAM0

MAP_SDRAM1
    ldr     r0, =(EXC_REGISTERS_BASE + 0xB4)        ;-Map SRAM1
    ldr     r1, =(EXC_SDRAM_BLOCK1_BASE + 0xC81)    ;  by loading register
    str     r1, [r0]                                ;  MMAP_SRAM1
     
MAP_PLD0
    ldr     r0, =(EXC_REGISTERS_BASE + 0xD0)        ;-Map PLD0
    ldr     r1, =(EXC_PLD_BLOCK0_BASE + 0x683)      ;  by loading register
    str     r1, [r0]                                ;  MMAP_PLD0
                                                            
COPY_CODE_TO_SRAM0                                                    
    ldr     r9,  =EXC_SPSRAM_BLOCK0_BASE            ;-Load base address of SRAM0
    ldr     r10, =EXC_EBI_BLOCK0_BASE               ;-Load base address of EBI0
    ldr     r12, =EXC_SPSRAM_BLOCK0_SIZE	             
    add     r11, r10, r12      			    ;-Load address of last