init.s

altera epxa1的例子程序

; 	Copyright ARM Ltd 1999. All rights reserved.
;
;	Based upon the ARM Developer Suite example embed/rom
;	Part's are:
; 	Copyright (c) Altera Corporation 2000.
; 	All rights reserved.
;
;
; 	This module maps in some on chip SRAM, initializes stack pointers and
; 	interrupts for each mode, and finally branches to __main in the C library (which
; 	eventually calls main()).
;
; 	On reset, the ARM core starts up in Supervisor (SVC) mode, in ARM state, with IRQ and FIQ disabled.

	    GET ..\stripe.s         ; megawizard generated defines, base addesses etc

        AREA    Init, CODE, READONLY

; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UNDEF      EQU     0x1B
Mode_SYS        EQU     0x1F ; available on ARM Arch 4 and later

I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled


; --- System memory locations
;
;	The stacks are setup as follows:
;	The supervisor mode stack is at the top of SRAM0 and is 256 bytes
;	The IRQ mode stack is the next 256 bytes and the USR stack
; 	is the next 256 bytes
;
;
;
; --- System memory locations
; We have mapped 256k of SRAM at address 0x000000 I'm using the top of
; block0 of this memory as a stack
RAM_Limit       EQU     EXC_SPSRAM_BLOCK1_BASE + EXC_SPSRAM_BLOCK1_SIZE
FIQ_Stack       EQU     RAM_Limit           ; 1k FIQ stack
IRQ_Stack       EQU     FIQ_Stack-1024      ; followed by  8k IRQ stack
SVC_Stack       EQU     IRQ_Stack-8192      ; followed by SVC stack

        ENTRY

        EXPORT  Reset_Handler

Reset_Handler



; --- Initialise stack pointer registers
; Enter IRQ mode and set up the IRQ stack pointer
        MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
    	ldr	r13,=0
	ldr	r14,=0
        LDR     SP, =IRQ_Stack

; Enter FIQ mode and set up the FIQ stack pointer
        MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
        LDR     SP, =FIQ_Stack

; Enter SVC mode and set up the SVC stack pointer
        MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
        LDR     SP, =SVC_Stack

; Set up other stack pointers if necessary
        ; ...

; --- Initialise memory system
        ; ...

	; Turn on the instruction cache
;	MRC 	p15,0,r0,c1,c0,0
;	LDR	r1,=0x80001078
;	ORRS	r0,r0,r1
;	MCR 	p15,0,r0,c1,c0,0

; --- Initialise critical IO devices
        ; ...

; --- Initialise interrupt system variables here
        ; ...


        IMPORT  __rt_entry

; --- Now enter the C code
        B      __rt_entry   ; note use B not BL, because an application will never return this way


        END