stripe_bb.v

altera epxa1的例子程序

// ARM-Based Excalibur black box instance for synthesis tools.
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ARM-Based Excalibur
// PROJECT: remote_reconfiguration
// ============================================================
// File Name: D:\DATA\projects\mutiple_pld_images\remote_reconfiguration\stripe_bb.v
// Megafunction Name(s): ARM-Based Excalibur
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// 
// Copyright (C) 1991-2002 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.
// 

module stripe
(
	clk_ref,
	npor,
	nreset,
	uartrxd,
	uartdsrn,
	uartctsn,
	uartrin,
	uartdcdn,
	uarttxd,
	uartrtsn,
	uartdtrn,
	intextpin,
	ebiack,
	ebidq,
	ebiclk,
	ebiwen,
	ebioen,
	ebiaddr,
	ebibe,
	ebicsn,
	sdramdq,
	sdramdqs,
	sdramclk,
	sdramclkn,
	sdramclke,
	sdramwen,
	sdramcasn,
	sdramrasn,
	sdramaddr,
	sdramcsn,
	sdramdqm,
	slavehclk,
	slavehwrite,
	slavehreadyi,
	slavehselreg,
	slavehsel,
	slavehmastlock,
	slavehaddr,
	slavehtrans,
	slavehsize,
	slavehburst,
	slavehwdata,
	slavehreadyo,
	slavebuserrint,
	slavehresp,
	slavehrdata,
	masterhclk,
	masterhready,
	masterhgrant,
	masterhrdata,
	masterhresp,
	masterhwrite,
	masterhlock,
	masterhbusreq,
	masterhaddr,
	masterhburst,
	masterhsize,
	masterhtrans,
	masterhwdata,
	intpld
);

input	clk_ref;
input	npor;
inout	nreset;
input	uartrxd;
input	uartdsrn;
input	uartctsn;
inout	uartrin;
inout	uartdcdn;
output	uarttxd;
output	uartrtsn;
output	uartdtrn;
input	intextpin;
input	ebiack;
inout	[15:0] ebidq;
output	ebiclk;
output	ebiwen;
output	ebioen;
output	[24:0] ebiaddr;
output	[1:0] ebibe;
output	[3:0] ebicsn;
inout	[31:0] sdramdq;
inout	[3:0] sdramdqs;
output	sdramclk;
output	sdramclkn;
output	sdramclke;
output	sdramwen;
output	sdramcasn;
output	sdramrasn;
output	[14:0] sdramaddr;
output	[1:0] sdramcsn;
output	[3:0] sdramdqm;
input	slavehclk;
input	slavehwrite;
input	slavehreadyi;
input	slavehselreg;
input	slavehsel;
input	slavehmastlock;
input	[31:0] slavehaddr;
input	[1:0] slavehtrans;
input	[1:0] slavehsize;
input	[2:0] slavehburst;
input	[31:0] slavehwdata;
output	slavehreadyo;
output	slavebuserrint;
output	[1:0] slavehresp;
output	[31:0] slavehrdata;
input	masterhclk;
input	masterhready;
input	masterhgrant;
input	[31:0] masterhrdata;
input	[1:0] masterhresp;
output	masterhwrite;
output	masterhlock;
output	masterhbusreq;
output	[31:0] masterhaddr;
output	[2:0] masterhburst;
output	[1:0] masterhsize;
output	[1:0] masterhtrans;
output	[31:0] masterhwdata;
input	[5:0] intpld;

endmodule