ethernet_recon_top.v

altera epxa1的例子程序

`define UART  1
`define SDRAM 1
`define FLASH 1

module remote_reconfiguration (

// stripe pins
	    clk_ref,
	    npor,
	    nreset,

// adam stuff
        ahb_hclk,
        ahb_hreset_n,

// stripe flash
`ifdef FLASH
	    intextpin,
    	ebiack,
	    ebidq,
    	ebiclk,
	    ebiwen,
    	ebioen,
	    ebiaddr,
    	ebibe,
	    ebicsn,
`endif

// stripe uart
`ifdef UART
    	uartrxd,
	    uartdsrn,
    	uartctsn,
	    uartrin,
    	uartdcdn,
	    uarttxd,
    	uartrtsn,
	    uartdtrn,
`endif

// stripe sdram
`ifdef SDRAM
	    sdramdq,
    	sdramdqs,
	    sdramclk,
    	sdramclkn,
	    sdramclke,
    	sdramwen,
	    sdramcasn,
    	sdramrasn,
	    sdramaddr,
    	sdramcsn,
	    sdramdqm,
`endif

// the MII interface
        mii_txcol,
        mii_txclk,
        mii_txd,
        mii_txen,
        mii_txer,

        mii_rxcrs,
        mii_rxclk,
        mii_rxd,
        mii_rxdv,
        mii_rxer,

        mii_mdclk,
        mii_mdio,
/*  these aren't connected on XA10 dev board
        mii_conn,
        mii_fd_n,
        mii_100m_n,
        mii_link_n,
*/
        mii_int_n           // added

// the EEPROM interface
/* these aren't connected on XA10 dev board
        prom_di,
        prom_do,
        prom_clk,
        prom_cs,
*/

// the External CAM interface
/* these aren't connected on XA10 dev board
        cam_load,
        cam_hit_n
*/

);  // module demo


input clk_ref;
inout nreset;
input npor;


// ADAM stuff
input           ahb_hclk;
input           ahb_hreset_n;

// the MII interface
input           mii_txcol;
input           mii_txclk;
output [3:0]    mii_txd;
output          mii_txen;
output          mii_txer;

input           mii_rxcrs;
input           mii_rxclk;
input [3:0]     mii_rxd;
input           mii_rxdv;
input           mii_rxer;

output          mii_mdclk;
inout           mii_mdio;

/* these aren't connected on XA10 dev board
input           mii_conn;
input           mii_fd_n;
input           mii_100m_n;
input           mii_link_n;
*/
input           mii_int_n;

// the EEPROM interface
/* these aren't connected on XA10 dev board
input           prom_di;
output          prom_do;
output          prom_clk;
output          prom_cs;
*/

// the External CAM interface
/* these aren't connected on XA10 dev board
output          cam_load;
input           cam_hit_n;
*/

// stripe uart
`ifdef UART
input           uartrxd;
input           uartdsrn;
input           uartctsn;
inout           uartrin;
inout           uartdcdn;
output          uarttxd;
output          uartrtsn;
output          uartdtrn;
`endif

// stripe flash
`ifdef FLASH
input           intextpin;
input           ebiack;
inout [15:0]    ebidq;
output          ebiclk;
output          ebiwen;
output          ebioen;
output [24:0]   ebiaddr;
output [1:0]    ebibe;
output [3:0]    ebicsn;
`endif

// stripe sdram
`ifdef SDRAM
inout [31:0]    sdramdq;
inout [3:0]     sdramdqs;
output          sdramclk;
output          sdramclkn;
output          sdramclke;
output          sdramwen;
output          sdramcasn;
output          sdramrasn;
output [14:0]   sdramaddr;
output [1:0]    sdramcsn;
output [3:0]    sdramdqm;
`endif



// the AHB System interface
wire            ahb_hclk;
wire            ahb_hreset_n;
wire            ahb_hirq;


// ahb 0, stripe
wire            nc_ahb_hbusreq0;
wire            nc_ahb_hlock0;

wire [31:0]     ahb_haddr0;
wire [31:0]     ahb_hwdata0;
wire [31:0]     ahb_hrdata0;
wire [1:0]      ahb_htrans0;
wire [2:0]      ahb_hburst0;
wire            ahb_hwrite0;
wire [2:0]      ahb_hsize0;
wire            ahb_hready0;
wire [1:0]      ahb_hresp0;


// ahb1, ethernet
wire            nc_ahb_hbusreq1;
wire            nc_ahb_hlock1;

wire [31:0]     ahb_haddr1;
wire [31:0]     ahb_hwdata1;
wire [31:0]     ahb_hrdata1;
wire [1:0]      ahb_htrans1;
wire [2:0]      ahb_hburst1;
wire            ahb_hwrite1;
wire [2:0]      ahb_hsize1;
wire            ahb_hready1;
wire [1:0]      ahb_hresp1;

// misc
wire            mii_conn = 1'b1;        // disable mii status signals
wire            mii_fd_n = 1'b1;
wire            mii_100m_n = 1'b1;
wire            mii_link_n = 1'b1;
wire            mii_int_n;
wire            prom_di = 1'b0;
wire            prom_do;
wire            prom_clk;
wire            prom_cs;
wire            cam_load;
wire            cam_hit_n = 1'b1;


// stripe uart
`ifdef UART
wire            uartrxd;
wire            uartdsrn;
wire            uartctsn;
wire            uartrin;
wire            uartdcdn;
wire            uarttxd;
wire            uartrtsn;
wire            uartdtrn;
`endif

// stripe flash
`ifdef FLASH
wire            ebiack;
tri [15:0]      ebidq;
wire            ebiclk;
wire            ebiwen;
wire            ebioen;
wire [24:0]     ebiaddr;
wire [1:0]      ebibe;
wire [3:0]      ebicsn;
`endif

// stripe sdram
`ifdef SDRAM
tri [31:0]      sdramdq;
tri [3:0]       sdramdqs;
wire            sdramclk;
wire            sdramclkn;
wire            sdramclke;
wire            sdramwen;
wire            sdramcasn;
wire            sdramrasn;
wire [14:0]     sdramaddr;
wire [1:0]      sdramcsn;
wire [3:0]      sdramdqm;
`endif




stripe stripe
(
	.clk_ref        ( clk_ref ),
	.npor           ( npor ),
	.nreset         ( nreset ),

// ahb 1 - stripe slave
	.slavehclk      ( ahb_hclk ),
	.slavehmastlock ( 1'b0 ),
	.slavebuserrint ( nc_1 ),

	.slavehselreg   ( 1'b0 ),
	.slavehsel      ( 1'b1 ),
	.slavehaddr     ( ahb_haddr1 ),
	.slavehwdata    ( ahb_hwdata1 ),
	.slavehrdata    ( ahb_hrdata1 ),
	.slavehtrans    ( ahb_htrans1 ),
	.slavehwrite    ( ahb_hwrite1 ),
	.slavehsize     ( ahb_hsize1[1:0] ),
	.slavehburst    ( ahb_hburst1 ),
	.slavehreadyi   ( ahb_hready1 ),
	.slavehreadyo   ( ahb_hready1 ),
	.slavehresp     ( ahb_hresp1 ),

// ahb 0 - stripe master
	.masterhclk     ( ahb_hclk ),
	.masterhbusreq  ( nc_ahb_hbusreq0 ),
	.masterhgrant   ( 1'b1 ),
	.masterhlock    ( nc_ahb_hlock0 ),

	.masterhaddr    ( ahb_haddr0 ),
	.masterhwdata   ( ahb_hwdata0 ),
	.masterhrdata   ( ahb_hrdata0 ),
	.masterhtrans   ( ahb_htrans0 ),
	.masterhwrite   ( ahb_hwrite0 ),
	.masterhsize    ( ahb_hsize0[1:0] ),
	.masterhburst   ( ahb_hburst0 ),
	.masterhready   ( ahb_hready0 ),
	.masterhresp    ( ahb_hresp0 ),

// stripe uart
`ifdef UART
	.uartrxd        ( uartrxd ),
	.uartdsrn       ( uartdsrn ),
	.uartctsn       ( uartctsn ),
	.uartrin        ( uartrin ),
	.uartdcdn       ( uartdcdn ),
	.uarttxd        ( uarttxd ),
	.uartrtsn       ( uartrtsn ),
	.uartdtrn       ( uartdtrn ),
`endif

// stripe flash
`ifdef FLASH
	.intextpin      (intextpin),
	.ebiack         (ebiack),
	.ebidq          (ebidq),
	.ebiclk         (ebiclk),
	.ebiwen         (ebiwen),
	.ebioen         (ebioen),
	.ebiaddr        (ebiaddr),
	.ebibe          (ebibe),
	.ebicsn         (ebicsn),
`endif

// stripe sdram
`ifdef SDRAM
	.sdramdq        (sdramdq),
	.sdramdqs       (sdramdqs),
	.sdramclk       (sdramclk),
	.sdramclkn      (sdramclkn),
	.sdramclke      (sdramclke),
	.sdramwen       (sdramwen),
	.sdramcasn      (sdramcasn),
	.sdramrasn      (sdramrasn),
	.sdramaddr      (sdramaddr),
	.sdramcsn       (sdramcsn),
	.sdramdqm       (sdramdqm),
`endif

	.intpld         ( {3'b0, ~mii_int_n, ahb_hirq, 1'b0} )
);
assign ahb_hsize0[2] = 1'b0;        // the stripe only has 2 ahb_hsize pins



ethernet_mac ethernet_mac (
// the AHB System interface
        .ahb_hclk       (ahb_hclk),
        .ahb_hreset_n   (ahb_hreset_n),
        .ahb_clkdiv     (2'b01),
        .ahb_bigendian  (1'b0),
        .ahb_hirq       (ahb_hirq),

// ahb 1 - ethernet master
        .ahb_m_hbusreq  (nc_ahb_hbusreq1),
        .ahb_m_hgrant   (1'b1),
        .ahb_m_hlock    (nc_ahb_hlock1),

        .ahb_m_haddr    (ahb_haddr1),
        .ahb_m_hwdata   (ahb_hwdata1),
        .ahb_m_hrdata   (ahb_hrdata1),
        .ahb_m_htrans   (ahb_htrans1),
        .ahb_m_hwrite   (ahb_hwrite1),
        .ahb_m_hsize    (ahb_hsize1),
        .ahb_m_hburst   (ahb_hburst1),
        .ahb_m_hready   (ahb_hready1),
        .ahb_m_hresp    (ahb_hresp1),

// ahb 0 - ethernet slave
        .ahb_s_hsel     (1'b1),
        .ahb_s_haddr    (ahb_haddr0[9:0]),
        .ahb_s_hwdata   (ahb_hwdata0),
        .ahb_s_hrdata   (ahb_hrdata0),
        .ahb_s_htrans   (ahb_htrans0),
        .ahb_s_hwrite   (ahb_hwrite0),
        .ahb_s_hsize    (ahb_hsize0),
        .ahb_s_hburst   (ahb_hburst0),
        .ahb_s_hready_in (ahb_hready0),
        .ahb_s_hready   (ahb_hready0),
        .ahb_s_hresp    (ahb_hresp0),

// the MII interface
        .mii_txcol      (mii_txcol),
        .mii_txclk      (mii_txclk),
        .mii_txd        (mii_txd),
        .mii_txen       (mii_txen),
        .mii_txer       (mii_txer),

        .mii_rxcrs      (mii_rxcrs),
        .mii_rxclk      (mii_rxclk),
        .mii_rxd        (mii_rxd),
        .mii_rxdv       (mii_rxdv),
        .mii_rxer       (mii_rxer),

        .mii_mdclk      (mii_mdclk),
        .mii_mdio       (mii_mdio),

        .mii_conn       (mii_conn),
        .mii_fd_n       (mii_fd_n),
        .mii_100m_n     (mii_100m_n),
        .mii_link_n     (mii_link_n),

// the EEPROM interface
        .prom_di        (prom_di),
        .prom_do        (prom_do),
        .prom_clk       (prom_clk),
        .prom_cs        (prom_cs),

// the External CAM interface
        .cam_load       (cam_load),
        .cam_hit_n      (cam_hit_n)
);  // adam


endmodule