📄 bootloader.s
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sub pc, pc, r0
add pc, pc, r0
nop ;-NOP is not executed as
; pipeline is flushed
; when pc is altered.
MAP_EBI1 ;now that code is in ram we can remap EBI1
ldr r0, =(EXC_REGISTERS_BASE + 0xC4) ;-Map EBI1
ldr r1, =(EXC_EBI_BLOCK1_BASE +0xA83) ; by loading register
str r1, [r0] ; MMAP_EBI1
EBI_BLOCK1
ldr r0, =(EXC_REGISTERS_BASE + 0x394) ;-Set options for EBI Block1
ldr r1, =0x01E ; by loading register
str r1, [r0] ; EBI_block1
;***************************************************************************
; Setup Stripe IO
;
; Much of the Embedded Stripe I/O is dual purpose, meaning if the Stripe
; does not need it, it can be used as regular PLD I/O. This section sets
; up the SDRAM and EBI and the UART pins for stripe use.
;***************************************************************************
ldr r0, =(EXC_REGISTERS_BASE + 0x40) ;-Load register
ldr r1, =0x7 ; IOCR_SDRAM
str r1, [r0] ; Fast slew rate, LVTTL,
; Stripe use
ldr r0, =(EXC_REGISTERS_BASE + 0x44) ;-Load register
ldr r1, =0x3 ; IOCR_EBI
str r1, [r0] ; Slow slew rate, LVTTL,
; Stripe use
ldr r0, =(EXC_REGISTERS_BASE + 0x48) ;-Load register
ldr r1, =0x3 ; IOCR_UART
str r1, [r0] ; Fast slew rate, LVTTL,
; PLD use
;***************************************************************************
; Configure PLD
; This section configures the PLD. The SBI data is appended to the end of the
; read only section of the code in the load view. In the execution view it
; resides at the address of (|Image$$Read_Only$$Limit| + EXC_EBI_BLOCK0_BASE)
; See the sbi_data section at the end of this file.
;
;***************************************************************************
CONFIGURE_PLD
ldr r0, =(EXC_REGISTERS_BASE + 0x144) ;-Set config_clock period
ldr r1, =0x4 ; to 7.8125MHz with
str r1, [r0] ; CONFIG_CLOCK reg (AHB2/8)
ldr r0, =(EXC_REGISTERS_BASE + 0x140) ;-Check Lock bit of
ldr r1, [r0] ; CONFIG_CONTROL
and r2, r1, #0x1
cmp r2, #0x1
beq PLD_LOCKED
orr r2, r1, #0x2 ;-Set CO bit of
str r2, [r0] ; CONFIG_CONTROL
ldr r0,=sbi_start ;-Set address of sbi_start
ldr r1, =(EXC_REGISTERS_BASE + 0x8) ;-Load address of IDCODE reg
ldr r2, [r1] ;-Load IDCODE from device
ldr r3, [r0, #4] ;-Load IDCODE from SBI file
cmp r2, r3 ;-Compare two IDCODE's
bne SBI_IDCODE_ERROR ;-Take error vector if two
; IDCODE's dont match
ldr r0,=sbi_start ;-Now look at flash copy of SBI
ldmia r0,{r1-r4} ;-Load the first 4 words
add r3, r3, r0 ;-Add coffset to get address of
; first word of config data
add r0, r3, r4 ;-Add csize to get address of
; last word of config data
ldr r2, =(EXC_REGISTERS_BASE + 0x148) ;-Load address of CONFIG_DATA
; register
ldr r4, =(EXC_REGISTERS_BASE + 0x140) ;-Load address of CONFIG_CONTROL
; register
ldr r5, =0x04 ;-Load Busy Bit mask
CONFIGURE_LOOP
ldr r1, [r3], #4 ;-Load a word of data
str r1, [r2] ;-Write data to CONFIG_DATA
BUSY_BIT_LOOP
ldr r6, [r4] ;-Load CONFIG_CONTROL
and r7, r6, r5 ;-Mask Busy Bit
cmp r7, #0x4 ;-Check if Busy Bit is set
beq BUSY_BIT_LOOP ;-If not, load more data
cmp r3, r0 ;-Loop until end of SBI file
bne CONFIGURE_LOOP
WAIT_FOR_CO_TO_BE_CLEARED ;-Wait for CO bit to be cleared
ldr r6, [r4] ;-Load CONFIG_CONTROL reg
and r6, r6, #0x2 ;-Mask CO bit
cmp r6, #0x2 ;-Loop until CO is '0'
beq WAIT_FOR_CO_TO_BE_CLEARED
CHECK_ERROR_BIT ;-Check E bit
and r7, r6, #0x010 ;-Mask E Bit
cmp r7, #0x010 ;-Take error vector if '1'
beq CONFIG_ERROR
;-PLD should now be in
; user mode.
PLD_CONFIG_DONE
;***************************************************************************
; Branch to application code
;***************************************************************************
b Reset_Handler ;Boot Default Application
;***************************************************************************
; WAIT_FUNCTION
;
; This function waits for a specified number of AHB1 cycles by reading the
; register AHB1_COUNT.
;
; r9 - Parameter that contains number of AHB1 cycles to wait
;
;***************************************************************************
WAIT_FUNCTION
ldr r7, [r6] ;-Load value of AHB1_COUNT
add r7, r7, r9 ;-r9 contains cycles to wait
; Load r7 with terminal count
WAIT_LOOP
ldr r8, [r6] ;-Load value of AHB1_COUNT
cmp r7, r8 ;-Compare to terminal count
bhi WAIT_LOOP ;-Loop until we get there
mov pc, lr ;-Return from function
;***************************************************************************
; Error Vectors
;
; These are the error vectors taken when errors are encountered in the boot
; process. These handlers simply trap the execution of code with an
; infinite loop.
;
;***************************************************************************
PLD_LOCKED ;-Error vector if PLD is locked
b PLD_LOCKED
CONFIG_ERROR ;-Error vector if PLD config
b CONFIG_ERROR ; sets error flag
ID_Error ;-Error vector if IDCODE does
b ID_Error ; not match expected value
SBI_IDCODE_ERROR ;-Error vector if IDCODE does
b SBI_IDCODE_ERROR ; not match SBI file
;***************************************************************************
; Interrupt Handlers
;
; These are the interrupt handlers that are run when interrupts are
; encountered. These handlers simply trap the execution of code with an
; infinite loop. It is the users responsibility to design meaningful
; interrupt handlers.
;
;***************************************************************************
UDEFHND
stmdb sp!,{r0-r12,lr}
bl CUdefHandler
ldmia sp!,{r0-r12,lr}
subs pc,lr,#4
SWIHND
stmdb sp!,{r0-r12,lr}
subs r0, lr, #4
ldr r0,[r0]
mov r1, #0xffffff
and r0,r0,r1
cmp r0, #1
beq Enable_IRQ_SWI
b EndOfSwi
Enable_IRQ_SWI
; Enable interrupts for User Mode
mrs r1,spsr
mvn r0,#0xc0
and r1,r1,r0
msr spsr_c,r1
b EndOfSwi
EndOfSwi
ldmia sp!,{r0-r12,lr}
movs pc, lr
PABTHND
stmdb sp!,{r0-r12,lr}
bl CPabtHandler
ldmia sp!,{r0-r12,lr}
subs pc,lr,#4
DABTHND
stmdb sp!,{r0-r12,lr}
bl CDabtHandler
ldmia sp!,{r0-r12,lr}
subs pc,lr,#4
UNEXPECTED
b UNEXPECTED
IRQHND
stmdb sp!,{r0-r12,lr}
bl CIrqHandler
ldmia sp!,{r0-r12,lr}
subs pc,lr,#4
FIQHND
stmdb sp!,{r0-r7,lr}
bl CFiqHandler
ldmia sp!,{r0-r7,lr}
subs pc,lr,#4
;***************************************************************************
; Include SBI file
;
; In this section, a new data section named sbi_data is declared. The
; INCBIN directive tells the assembler to insert the file boot_example.sbi
; in pure binary form. The file is not interpreted in any way. During
; the PLD configuration portion of the boot process, this file is read
; using the sbi_start label. The SBI file is written to the PLD
; configuration peripheral to configure the PLD portion of the device.
;
;***************************************************************************
AREA sbi_data, DATA, READONLY
sbi_start
INCBIN Simple_Excalibur_System.sbi
sbi_end
;***************************************************************************
; End of assembly source file
;***************************************************************************
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