init.s

altera epxa1的例子程序

; 	Copyright ARM Ltd 1999. All rights reserved.
;
;	Based upon the ARM Developer Suite example embed/rom
;	Part's are:
; 	Copyright (c) Altera Corporation 2000.
; 	All rights reserved.
;
;
; 	This module maps in some on chip SRAM, initializes stack pointers and
; 	interrupts for each mode, and finally branches to __main in the C library (which
; 	eventually calls main()).
;
; 	On reset, the ARM core starts up in Supervisor (SVC) mode, in ARM state, with IRQ and FIQ disabled.

	    GET stripe.s         ; megawizard generated defines, base addesses etc
	    

        AREA    c_init, CODE, READONLY

; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UNDEF      EQU     0x1B
Mode_SYS        EQU     0x1F ; available on ARM Arch 4 and later

I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled


; --- System memory locations
;
;	The stacks are setup as follows:
;	The supervisor mode stack is at the top of SRAM0 and is 256 bytes
;	The IRQ mode stack is the next 256 bytes and the USR stack
; 	is the next 256 bytes
;
;
;
; --- System memory locations
; We have mapped 256k of SRAM at address 0x100000 I'm using the top of 
; this memory as a stack
RAM_Limit       EQU     EXC_SPSRAM_BLOCK1_BASE + EXC_SPSRAM_BLOCK1_SIZE 

SVC_Stack       EQU     RAM_Limit           ; 8K SVC stack at top of memory
IRQ_Stack       EQU     RAM_Limit-8192      ; followed by  1k IRQ stack
ABT_Stack       EQU     IRQ_Stack-1024      ; followed by  1k ABT stack 
FIQ_Stack		EQU		ABT_Stack-1024		; followed by  1k FIQ stack 
UNDEF_Stack		EQU		FIQ_Stack-1024		; followed by  1k UNDEF stack 
USR_Stack       EQU     UNDEF_Stack-1024    ; followed by  USR stack


      

        EXPORT  Reset_Handler

Reset_Handler 

; Turn on the instruction cache
	MRC 	p15,0,r0,c1,c0,0
	LDR	r1,=0x80001078
	ORRS	r0,r0,r1
	MCR 	p15,0,r0,c1,c0,0
	
	; --- Initialise stack pointer registers
; Enter SVC mode and set up the SVC stack pointer
        MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
        LDR     SP, =SVC_Stack

; Enter IRQ mode and set up the IRQ stack pointer
        MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
        LDR     SP, =IRQ_Stack

; Enter FIQ mode and set up the FIQ stack pointer
        MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
        LDR     SP, =FIQ_Stack

; Enter UNDEF mode and set up the UNDEF stack pointer
        MSR     CPSR_c, #Mode_UNDEF:OR:I_Bit:OR:F_Bit ; No interrupts
        LDR     SP, =UNDEF_Stack

; Enter ABT mode and set up the ABT stack pointer
        MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts
        LDR     SP, =ABT_Stack
        ; ...

; --- Now change to User mode and set up User mode stack.
        MSR     CPSR_c, #Mode_USR:OR:I_Bit:OR:F_Bit ; No interrupts
        LDR     SP, =USR_Stack
        
; --- Initialise memory system
        ; ...

	

; --- Initialise critical IO devices
        ; ...

; --- Initialise interrupt system variables here
	
; --- Now change to User mode and set up User mode stack.
     
        IMPORT  __rt_entry

; --- Now enter the C code
        B      __rt_entry  ; note use B not BL, because an application will never return this way


;******************************************************************************
;*
;*		Useful admin functions
;*		======================
;*
;*		Author:	PRR
;*
;******************************************************************************/

	EXPORT EnableIRQ

	AREA |C$$Code|,CODE,READONLY
	
;
;	The ARM C runtime code puts us into User mode, to enable interrupts
; 	we need to be in supervisor mode, so use a SWI to do this
;	
EnableIRQ
	SWI 1	
	mov	pc, lr
	
	END

	AREA |Stacks|, DATA, NOINIT
	%	8192
SvcStackTop	
	%	1024
IrqStackTop	
	%	1024
FiqStackTop
	%	1024
AbtStackTop	
	%	1024
UndefStackTop	
        END