priority_encoder.v

来自「altera epxa1的例子程序」· Verilog 代码 · 共 28 行

/****************************************************
 *	MODULE:		priority_encoder					*
 *	AUTHOR:		ORC									*
 *	CODE TYPE:	Behavioral							*
 *	DESCRIPTION: 10-to-4 priority encoder			*
 ****************************************************/

module priority_encoder ( in, out);

input [9:1] in;  
output [4:1] out;

always @(in)
	casex (in)
		9'b1xxxxxxxx: out = 4'b1001;
		9'b01xxxxxxx: out = 4'b1000;
		9'b001xxxxxx: out = 4'b0111;
		9'b0001xxxxx: out = 4'b0110;
		9'b00001xxxx: out = 4'b0101;
		9'b000001xxx: out = 4'b0100;
		9'b0000001xx: out = 4'b0011;
		9'b00000001x: out = 4'b0010;
		9'b000000001: out = 4'b0001;
		9'b000000000: out = 4'b0000;		
	endcase

endmodule