irq.c

altera epxa1的例子程序

/*
*   Initializes the stripe interrupt controller for 6 individual interrupt mode.
*	Also handles IRQ and FIQ interrupts.
*
*	Author: ORC
*
*   Copyright (c) Altera Corporation 2000-2001.
*   All rights reserved.
*/

#include <stdio.h>
#include "stripe.h"
#include "int_ctrl00.h"
#include "uartcomm.h"
#include "irq.h"
#include "timer.h"

// Initialize the stripe interrupt controller 
void irq_init(void)
{	
	// Set priority for INT_PLD interrupts.
	// INT_PLD[0] generates a FIQ interrupt, while
	// INT_PLD[5-1] generate an IRQ interrupt.		
	*INT_PRIORITY_P0(EXC_INT_CTRL00_BASE) = PLDINT0_FIQ_PRI;	
	*INT_PRIORITY_P1(EXC_INT_CTRL00_BASE) = PLDINT1_IRQ_PRI;
	*INT_PRIORITY_P2(EXC_INT_CTRL00_BASE) = PLDINT2_IRQ_PRI;
	*INT_PRIORITY_P3(EXC_INT_CTRL00_BASE) = PLDINT3_IRQ_PRI;	
	*INT_PRIORITY_P4(EXC_INT_CTRL00_BASE) = PLDINT4_IRQ_PRI;
	*INT_PRIORITY_P5(EXC_INT_CTRL00_BASE) = PLDINT5_IRQ_PRI;
	
	// Set priority for UART interrupt
	*INT_PRIORITY_UA(EXC_INT_CTRL00_BASE) = UART_IRQ_PRI;
	
	// Enable UART and INT_PLD interrupt
	*INT_MS(EXC_INT_CTRL00_BASE) = 	INT_MS_UA_MSK |
									INT_MS_P0_MSK | INT_MS_P1_MSK | INT_MS_P2_MSK |
						   		    INT_MS_P3_MSK | INT_MS_P4_MSK | INT_MS_P5_MSK;	
}

// Process the pending interrupts depending on their interrupt mode
void CIrqHandler(void)
{	
	volatile unsigned int irqID;

	// Read the Interrupt Identity register for the highest priority interrupt that is active and enabled
	irqID = *INT_ID(EXC_INT_CTRL00_BASE) & INT_ID_ID_MSK;

	// Jump to interrupt handler that is currently pending
	switch (irqID)
	{	
		case PLDINT1_IRQ_PRI:
			pldint1_irq_handler();
			break;

		case PLDINT2_IRQ_PRI:
			pldint2_irq_handler();
			break;

		case PLDINT3_IRQ_PRI:
			pldint3_irq_handler();
			break;	
	
		case PLDINT4_IRQ_PRI:
			pldint4_irq_handler();
			break;
	
		case PLDINT5_IRQ_PRI:
			pldint5_irq_handler();
			break;
		
		case UART_IRQ_PRI:
			uart_irq_handler();
			break;

		default:
			// Clear unexpected INT_PLD interrupt
			*INT_CLR(EXC_PLD_BLOCK0_BASE) = irqID;										
			break;
	}
	return;
}

// Process pending FIQ interrupt
void CFiqHandler(void)
{	
	// Clear INT_PLD[0] interrupt by writing to a PLD slave register to deactivate that signal
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P0_MSK;
	
	// Store INT_PLD[0] occurrance to a buffer
	if (count < LIMIT)
		buffer[count++] = PLDINT0_FIQ_PRI;	
	return;
}

// Process pending INT_PLD[1] interrupt
void pldint1_irq_handler(void)
{
	// Clear INT_PLD[1] interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P1_MSK; 

	// Store INT_PLD[1] occurrance to a buffer
	if (count < LIMIT)
		buffer[count++] = PLDINT1_IRQ_PRI;
	return;	
}

// Process pending INT_PLD[2] interrupt
void pldint2_irq_handler(void)
{
	// Clear INT_PLD[2] interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P2_MSK; 

	// Store INT_PLD[2] occurrance to a buffer
	if (count < LIMIT)
		buffer[count++] = PLDINT2_IRQ_PRI;
	return;		
}

// Process pending INT_PLD[3] interrupt
void pldint3_irq_handler(void)
{
	// Clear INT_PLD[3] interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P3_MSK;	

	// Store INT_PLD[3] occurrance to a buffer
	if (count < LIMIT)
		buffer[count++] = PLDINT3_IRQ_PRI;
	return;	
}

// Process pending INT_PLD[4] interrupt
void pldint4_irq_handler(void)
{
	// Clear INT_PLD[4] interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P4_MSK; 

	// Store INT_PLD[4] occurrance to a buffer
	if (count < LIMIT)
		buffer[count++] = PLDINT4_IRQ_PRI;
	return;		
}

// Process pending INT_PLD[5] interrupt
void pldint5_irq_handler(void)
{
	// Clear INT_PLD[5] interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P5_MSK; 

	// Store INT_PLD[5] occurrance to a buffer
	if (count < LIMIT)
		buffer[count++] = PLDINT5_IRQ_PRI;
	return;		
}