irq.c

altera epxa1的例子程序

/*
*   Initializes the stripe interrupt controller for 5-bit priority mode.
* 	Also handles IRQ and FIQ interrupts.
*
*	Author: ORC
*
*   Copyright (c) Altera Corporation 2000-2001.
*   All rights reserved.
*/

#include <stdio.h>
#include "stripe.h"
#include "int_ctrl00.h"
#include "uartcomm.h"
#include "irq.h"
#include "timer.h"

// Initialize the stripe interrupt controller 
void irq_init(void)
{
	// Set interrupt mode to 5-bit priority
	*INT_MODE(EXC_INT_CTRL00_BASE) = INT_MODE_FIVE_PRI;
	
	// Set priority for UART interrupt
	*INT_PRIORITY_UA(EXC_INT_CTRL00_BASE) = UART_IRQ_PRI;
	
	// Set priority for INT_PLD[0] interrupt		
	*INT_PRIORITY_P0(EXC_INT_CTRL00_BASE) = PLDINT0_FIQ_PRI;

	// Enable UART and INT_PLD[0] interrupts
	*INT_MS(EXC_INT_CTRL00_BASE) = INT_MS_UA_MSK | INT_MS_P0_MSK;
}

// Enable PLD interrupts by setting it MASK bits
void enable_pld_int(void)
{
	// Enable PLD interrupts by writing to a PLD slave register to activate that signal
	*INT_MASK(EXC_PLD_BLOCK0_BASE) = INT_MASK_P1_MSK | INT_MASK_P2_MSK | INT_MASK_P3_MSK |
									 INT_MASK_P4_MSK | INT_MASK_P5_MSK | INT_MASK_P6_MSK |
									 INT_MASK_P7_MSK | INT_MASK_P8_MSK | INT_MASK_P9_MSK;
}

// Disable PLD interrupts by clearing its MASK bits
void disable_pld_int(void)
{
	// Disable PLD interrupts by writing to a PLD slave register to deactivate that signal
	*INT_MASK(EXC_PLD_BLOCK0_BASE) = 0x0;
}

// Process pending IRQ interrupts
void CIrqHandler(void)
{	
	volatile unsigned int irqID;
	
	// Read the Interrupt Identity register for the highest priority interrupt that is active and enabled
	irqID = *INT_ID(EXC_INT_CTRL00_BASE) & INT_ID_ID_MSK;

	// Jump to interrupt handler that is currently pending
	switch (irqID)
	{		
		case UART_IRQ_PRI:
			uart_irq_handler();
			break;

		case INT1_IRQ_PRI:
			int1_irq_handler();
			break;	

		case INT2_IRQ_PRI:
			int2_irq_handler();
			break;		
	
		case INT3_IRQ_PRI:
			int3_irq_handler();
			break;	

		case INT4_IRQ_PRI:
			int4_irq_handler();
			break;					

		case INT5_IRQ_PRI:
			int5_irq_handler();	
			break;	
			
		case INT6_IRQ_PRI:
			int6_irq_handler();	
			break;	
			
		case INT7_IRQ_PRI:
			int7_irq_handler();	
			break;	
			
		case INT8_IRQ_PRI:
			int8_irq_handler();
			break;	
						
		case INT9_IRQ_PRI:
			int9_irq_handler();				
			break;						
	}

	return;
}

// Process pending FIQ interrupt
void CFiqHandler(void)
{	
	// Clear INT_PLD[0] interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P0_MSK;
	
	// Store INT_PLD[0] occurrance to a buffer
	if (count < LIMIT)
		buffer[count++] = PLDINT0_FIQ_PRI;	
	return;
}

// Process pending INT1 interrupt
void int1_irq_handler(void)
{
	// Clear INT1 interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P1_MSK; 
	
	// Store INT1 occurrance to a buffer
	if (count < LIMIT)
		buffer[count++] = INT1_IRQ_PRI;	
	return;
}

// Process pending INT2 interrupt
void int2_irq_handler(void)
{
	// Clear INT2 interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P2_MSK;
	
	// Store INT2 occurrance to a buffer
	if (count < LIMIT)
		buffer[count++] = INT2_IRQ_PRI;	
	return;
}

// Process pending INT3 interrupt
void int3_irq_handler(void)
{
	// Clear INT3 interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P3_MSK;
	
	// Store INT3 occurrance to a buffer 
	if (count < LIMIT)
		buffer[count++] = INT3_IRQ_PRI;	
	return;
}

// Process pending INT4 interrupt
void int4_irq_handler(void)
{
	// Clear INT4 interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P4_MSK;
	
	// Store INT4 occurrance to a buffer 
	if (count < LIMIT)
		buffer[count++] = INT4_IRQ_PRI;	
	return;
}

// Process pending INT5 interrupt
void int5_irq_handler(void)
{
	// Clear INT5 interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P5_MSK; 

	// Store INT5 occurrance to a buffer
	if (count < LIMIT)
		buffer[count++] = INT5_IRQ_PRI;	
	return;
}

// Process pending INT6 interrupt
void int6_irq_handler(void)
{
	// Clear INT6 interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P6_MSK; 

	// Store INT6 occurrance to a buffer
	if (count < LIMIT)
		buffer[count++] = INT6_IRQ_PRI;
	return;
}

// Process pending INT7 interrupt
void int7_irq_handler(void)
{
	// Clear INT7 interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P7_MSK; 
	
	// Store INT7 occurrance to a buffer
	if (count < LIMIT)
		buffer[count++] = INT7_IRQ_PRI;	
	return;
}

// Process pending INT8 interrupt
void int8_irq_handler(void)
{
	// Clear INT8 interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P8_MSK; 
	
	// Store INT8 occurrance to a buffer
	if (count < LIMIT)
		buffer[count++] = INT8_IRQ_PRI;	
	return;
}

// Process pending INT9 interrupt
void int9_irq_handler(void)
{
	// Clear INT9 interrupt
	*INT_CLR(EXC_PLD_BLOCK0_BASE) = INT_CLR_P9_MSK; 
	
	// Store INT9 occurrance to a buffer
	if (count < LIMIT)
		buffer[count++] = INT9_IRQ_PRI;	
	return;
}