regfile.v

altera epxa1的例子程序

// Copyright (C) 1991-2001 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner.  Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors.  No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.

`include "ahb_include.v"

// TOP MODULE
module regfile (reset,
				address, 
			 	clock,
			    wdata,
			    rdata,
				write,
				clock_en,
				clr_int,
				mask_int
				);
// INPUTS
	input		  clock;			// regfile clock
	input		  clock_en;			// regfile clock enable
	input		  reset;			// reset
	input  [4:0]  address;			// Address bus 16 locations
	input  [31:0] wdata;			// Write data bus
	input		  write;			// High is write Low is read

// OUTPUTS	
	output [31:0] rdata;			// Read Data bus
	output [31:0] clr_int;			// Clear pending PLD interrupts 
	output [31:0] mask_int;			// Mask pending PLD interrupts
	
// Internal Declarations
	reg [31:0] rdata;
	reg [31:0] clr_int;
	reg [31:0] mask_int;	

// Main Code
	always @(posedge clock or negedge reset)
		if(~reset)
		  begin
			rdata <= 0;
			clr_int <= 0;
			mask_int <= 0;
			end
		else
			begin
			
			if (write && clock_en && address == 0)
				clr_int <= wdata;
			else
				clr_int <= 0;
				
			if (write && clock_en && address == 4)
				mask_int <= wdata;
			
			if (~write && clock_en)
				case(address)
					0: rdata <= 0; // clr_int
					4: rdata <= mask_int;
					default: rdata <= 0;
		  	endcase		

			end // posedge clock	

endmodule