multi_master_reference_design.s

altera epxa1的例子程序

; Copyright (C) 2000-2001 Altera Corporation
;-------------------------------------------------------------------------------------
; This code assumes that the chip's memory map and other register settings are at the
; values defined in memory.regs, memory.sram, memry.dpram
;-------------------------------------------------------------------------------------

	GET ../embedded_stripe.s
	EXPORT Entry
	AREA |Code|,CODE,READONLY

Entry
	b   Start
	b   Unexpected
	b   Unexpected
	b   Unexpected
	b   Unexpected
	b   Unexpected
	b   Unexpected

;; Unexpected exception handler
Unexpected
	b   Unexpected

;; Start of main program

Start
;;Load data to be transferred
   
    mov r0, #97		        ;;Load Data in r0 to be transferred
    mov r1, #1		        ;;Load Data in r1 to be transferred
    mov r2, #2		        ;;Load Data in r2 to be transferred
    mov r3, #3		        ;;Load Data in r3 to be transferred
    mov r4, #4		        ;;Load Data in r4 to be transferred
    mov r5, #5		        ;;Load Data in r5 to be transferred
    mov r6, #6		        ;;Load Data in r6 to be transferred
    mov r7, #7		        ;;Load Data in r7 to be transferred
    mov r8, #8		        ;;Load Data in r8 to be transferred
    

;;Single Write and Read to Slave 4 Single Transaction Slave
    
	ldr r12, =SLAVE4_BASE	;;Load the base address for Slave 4 in r12
	str r0, [r12]			;;Store data in base address of Slave 4
	ldr r9, [r12]			;;Read data back from Slave 4

;;Drive the ALU with the processor (slave 5 alu slave)
    
	ldr r12, =OPERAND1_REGISTER	 ;;Load the address for operand 1 in r12
	str r3, [r12]			     ;;Store the contents of r3 as operand 1
	
	ldr r12, =OPERAND2_REGISTER  ;;Load the address for operand 2 in r12
	str r4, [r12]			     ;;Store the contents of r4 as operand 2
	
	ldr r12, =OPERATION_REGISTER  ;;Load the address for the operation register in r12
	str r7, [r12]			      ;;Store the contents of r7 as operation(7 = MULT)
	
	ldr r12, =RESULT_LOW_REGISTER  ;;Load the address for the lower nibble of the result register in r12
	ldr r9, [r12]			       ;;Read back the result into register r9
	
;;Burst Write and Read to Slave 6 Burst Transaction Slave

    ldr r12, =SLAVE6_BASE	;;Load the base address for Slave 6 in r12
	stmia r12!, {r1-r8}	    ;;Write to Slave 6 a burst of 8 words
	;;Read the data back backwards
	sub r12, r12, #4        ;;Decrement the address by a word
	ldr r1, [r12]	        ;;Load the last value bursted 
	sub r12, r12, #4        
	ldr r2, [r12]
	sub r12, r12, #4
	ldr r3, [r12]
	sub r12, r12, #4
	ldr r4, [r12]
	sub r12, r12, #4
	ldr r5, [r12]
	sub r12, r12, #4
	ldr r6, [r12]
	sub r12, r12, #4
	ldr r7, [r12]
	sub r12, r12, #4
	ldr r8, [r12]
	
;;Single Write and Read to Slave 7 Single Transaction Slave
    
	ldr r12, =SLAVE7_BASE	;;Load the base address for Slave 7 in r12
	str r0, [r12]			;;Store data in base address of Slave 7
	ldr r9, [r12]			;;Read data back from Slave 7
	
;;Burst Write and Read to Slave 8 Burst Transaction Slave

    ldr r12, =SLAVE8_BASE	;;Load the base address for Slave 8 in r12
	stmia r12!, {r1-r8}	    ;;Write to Slave 8 a burst of 8 words
	;;Read the data back backwards
	sub r12, r12, #4        ;;Decrement the address by a word
	ldr r1, [r12]	        ;;Load the last value bursted 
	sub r12, r12, #4        
	ldr r2, [r12]
	sub r12, r12, #4
	ldr r3, [r12]
	sub r12, r12, #4
	ldr r4, [r12]
	sub r12, r12, #4
	ldr r5, [r12]
	sub r12, r12, #4
	ldr r6, [r12]
	sub r12, r12, #4
	ldr r7, [r12]
	sub r12, r12, #4
	ldr r8, [r12]
	
;;Burst Write and Read to Slave 9 Wide Transaction Slave
    ldr r12, =SLAVE9_BASE	;;Load the base address for Slave 9 in r12
	stmia r12!, {r1-r8}	    ;;Write to Slave 9 a burst of 8 words
	stmia r12!, {r1-r8}	    ;;Write to Slave 9 a burst of 8 words
	ldr r12, =SLAVE9_BASE	;;Load the base address for Slave 9 in r12
	ldmia r12!, {r1-r8}
	ldmia r12!, {r1-r8}
	
;;Burst Read from SRAM, Master 4 has loaded it with some data and the processor is now going to read it back
	
    ldr r12, =SRAM1_BASE	;;Load the base address for SRAM1 base in r12
	ldmia r12!, {r1-r8}	    ;;First 8 words in SRAM
	ldmia r12!, {r1-r8}	    ;;Second 8 words in SRAM
	

	nop	; The first few unused memory locations are padded to prevent unknown
	nop	; rom contents causing Xs in simulation waveform (not actually required)
	nop
	nop

;; Memory map for PLD Slaves 
SLAVE4_BASE   EQU     0x80010004
SLAVE5_BASE   EQU     0x80020000
SLAVE6_BASE   EQU     0x80040004
SLAVE7_BASE   EQU     0x80080004
SLAVE8_BASE   EQU     0x80100004
SLAVE9_BASE   EQU     0x80200008
SRAM1_BASE	  EQU	  0x90000004
OPERAND1_REGISTER      EQU     SLAVE5_BASE + 0x04
OPERAND2_REGISTER      EQU     SLAVE5_BASE + 0x08
OPERATION_REGISTER     EQU     SLAVE5_BASE + 0x0C
RESULT_LOW_REGISTER    EQU     SLAVE5_BASE + 0x10
RESULT_HIGH_REGISTER   EQU     SLAVE5_BASE + 0x14

	END