wave_interconnect_matrix.do

altera epxa1的例子程序

onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {PLD Bus1}
add wave -noupdate -format Literal /ahb_bus_tb/dut/pld_bus1_decoder/HSEL
add wave -noupdate -format Literal /ahb_bus_tb/dut/arbiter_pld_bus1/HMASTER
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Address_Control_mux_pld_bus1/HADDR
add wave -noupdate -format Literal /ahb_bus_tb/dut/Address_Control_mux_pld_bus1/HTRANS
add wave -noupdate -format Literal /ahb_bus_tb/dut/Address_Control_mux_pld_bus1/HSIZE
add wave -noupdate -format Literal /ahb_bus_tb/dut/Address_Control_mux_pld_bus1/HBURST
add wave -noupdate -format Logic /ahb_bus_tb/dut/Address_Control_mux_pld_bus1/HWRITE
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Write_data_bus_mux_pld_bus1/HWDATA
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Read_data_bus_and_Slave_Response_pld_bus1/HRDATA
add wave -noupdate -format Literal /ahb_bus_tb/dut/Read_data_bus_and_Slave_Response_pld_bus1/HRESP
add wave -noupdate -format Logic /ahb_bus_tb/dut/Read_data_bus_and_Slave_Response_pld_bus1/HREADY
add wave -noupdate -divider {PLD Bus2}
add wave -noupdate -format Literal /ahb_bus_tb/dut/pld_bus2_decoder/HSEL
add wave -noupdate -format Literal /ahb_bus_tb/dut/arbiter_pld_bus2/HMASTER
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Address_Control_mux_pld_bus2/HADDR
add wave -noupdate -format Literal /ahb_bus_tb/dut/Address_Control_mux_pld_bus2/HTRANS
add wave -noupdate -format Literal /ahb_bus_tb/dut/Address_Control_mux_pld_bus2/HSIZE
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Write_data_bus_mux_pld_bus2/HWDATA
add wave -noupdate -format Logic /ahb_bus_tb/dut/Address_Control_mux_pld_bus2/HWRITE
add wave -noupdate -format Literal /ahb_bus_tb/dut/Address_Control_mux_pld_bus2/HBURST
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Read_data_bus_and_Slave_Response_pld_bus2/HRDATA
add wave -noupdate -format Literal /ahb_bus_tb/dut/Read_data_bus_and_Slave_Response_pld_bus2/HRESP
add wave -noupdate -format Logic /ahb_bus_tb/dut/Read_data_bus_and_Slave_Response_pld_bus2/HREADY
add wave -noupdate -divider layer1
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/HSEL_layer1
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/HADDR_layer1
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/HTRANS_layer1
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/HSIZE_layer1
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/HBURST_layer1
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/HWRITE_layer1
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/HREADY_in_layer1
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/HWDATA_layer1
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/HREADY_out_slave1
add wave -noupdate -divider layer2
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/HSEL_layer2
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/HADDR_layer2
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/HTRANS_layer2
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/HSIZE_layer2
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/HBURST_layer2
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/HWRITE_layer2
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/HREADY_in_layer2
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/HWDATA_layer2
add wave -noupdate -divider {input stage layer1}
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HSEL_layer
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HADDR_layer
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HTRANS_layer
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HSIZE_layer
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HBURST_layer
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HWRITE_layer
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HWDATA_layer
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HREADY_slave
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HADDR_slave
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HTRANS_slave
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HSIZE_slave
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HBURST_slave
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HWRITE_slave
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HWDATA_slave
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HADDR_slave_reg
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HTRANS_slave_reg
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HSIZE_slave_reg
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HBURST_slave_reg
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HWRITE_slave_reg
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer1/HWDATA_slave_reg
add wave -noupdate -divider {input state layer2}
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HRESETn
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HCLOCK
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HSEL_layer
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HADDR_layer
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HTRANS_layer
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HSIZE_layer
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HBURST_layer
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HWRITE_layer
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HWDATA_layer
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HREADY_slave
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HADDR_slave
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HTRANS_slave
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HSIZE_slave
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HBURST_slave
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HWRITE_slave
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HWDATA_slave
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HREADY_slave_reg
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HADDR_slave_reg
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HTRANS_slave_reg
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HSIZE_slave_reg
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HBURST_slave_reg
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HWRITE_slave_reg
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/input_stage_layer2/HWDATA_slave_reg
add wave -noupdate -divider {interconnect mux slave1}
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HCLOCK
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HRESETn
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HADDR_layer1
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HTRANS_layer1
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HSIZE_layer1
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HBURST_layer1
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HWRITE_layer1
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HREADY_in_layer1
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HWDATA_layer1
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/layer1_req
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HADDR_layer2
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HTRANS_layer2
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HSIZE_layer2
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HBURST_layer2
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HWRITE_layer2
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HREADY_in_layer2
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HWDATA_layer2
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/layer2_req
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HADDR_slave
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HTRANS_slave
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HSIZE_slave
add wave -noupdate -format Literal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HBURST_slave
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HWRITE_slave
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HWDATA_slave
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/HREADY_in_slave
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/layer_granted_delay
add wave -noupdate -format Logic /ahb_bus_tb/dut/interconnect_matrix/interconnect_mux_slave1/layer_granted
add wave -noupdate -divider {interconnect mux slave2}
add wave -noupdate -format Literal /ahb_bus_tb/dut/arbiter_pld_bus2/HBUSREQ
add wave -noupdate -format Literal /ahb_bus_tb/dut/arbiter_pld_bus2/HGRANT