📄 isr_table.asm
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//---------------------------------------------------------------------------------------------------------
//
// (C) Copyright 2002 - Analog Devices, Inc. All rights reserved.
//
// File Name: ISR_table.asm
//
// Date Modified: 4/11/02 Rev 1.0
//
// Purpose: ADSP-21160 Interrupt Vector Table
//
//---------------------------------------------------------------------------------------------------------
#include <def21160.h>
.EXTERN _main;
.SEGMENT/PM seg_rth; // 21160 Interrupt Service Table
// 0x00 Reserved Interrupt
// 0x00 0x01 0x02 0x03
// nop; nop; nop; nop; // Reserved interrupt
// Vector for RESET:
// 0x04 - reset vector starts at location 0x40005
RSTI_scv: // IDLE; // Implicit IDLE instruction
nop;
nop;
jump _main;
// 0x08 - Vector address for illegal input condition detected
IICD_svc: rti;
rti;
rti;
rti;
// 0x0C - Vector address for status stack/loop stack overflow or PC stack full:
SOVFI_svc: rti;
rti;
rti;
rti;
// 0x10 - Vector address for high priority timer interrupt:
TMZHI_svc: rti;
rti;
rti;
rti;
// 0x14 - Vector address for Vector Interrupt:
VIRPTI_svc: rti;
rti;
rti;
rti;
// 0x18 - Vector address for Hardware Interrupt 2 (IRQ2):
IRQ2I_svc: rti;
rti;
rti;
rti;
// 0x1C - Vector address for Hardware Interrupt 1 (IRQ1):
IRQ1I_svc: rti;
rti;
rti;
rti;
// 0x20 - Vector address for Hardware Interrupt 0 (IRQ0):
IRQ0I_svc: rti;
rti;
rti;
rti;
// 0x24 - Reserved interrupt
reserved_0x24: nop;nop;nop;nop; // Reserved interrupt
// Vectors for Serial port DMA channels:
// 0x28 - Vector address for Serial Port 0 Receive (DMA Channel 0)
SPR0I_svc: rti;
rti;
rti;
rti;
// 0x2C - Vector address for Serial Port 1 Receive (DMA Channel 1)
SPR1I_svc: rti;
rti;
rti;
rti;
// 0x30 - Vector address for Serial Port 0 Transmit (DMA Channel 2)
SPT0I_svc: rti;
rti;
rti;
rti;
// 0x34 - Vector address for Serial Port 1 Transmit (DMA Channel 3)
SPT1I_svc: rti;
rti;
rti;
rti;
// Vectors for link port DMA channels:
// 0x38 - Vector address for Link Buffer 0 (DMA Channel 4)
LP0I_svc: rti;
rti;
rti;
rti;
// 0x3C - Vector address for Link Buffer 1 (DMA Channel 5)
LP1I_svc: rti;
rti;
rti;
rti;
// 0x40 - Vector address for Link Buffer 2 (DMA Channel 6)
LP2I_svc: rti;
rti;
rti;
rti;
// 0x44 - Vector address for Link Buffer 3 (DMA Channel 7)
LP3I_svc: rti;
rti;
rti;
rti;
// 0x48 - Vector address for Link Buffer 4 (DMA Channel 8)
LP4I_svc: rti;
rti;
rti;
rti;
// 0x4C - Vector address for Link Buffer 5 (DMA Channel 9)
LP5I_svc: rti;
rti;
rti;
rti;
// Vectors for External port DMA channels:
// 0x50 - Vector address for External Port Buffer 0 (DMA Channel 10)
EP0I_svc: rti;
rti;
rti;
rti;
// 0x54 - Vector address for External Port Buffer 0 (DMA Channel 11)
EP1I_svc: rti;
rti;
rti;
rti;
// 0x58 - Vector address for External Port Buffer 0 (DMA Channel 12)
EP2I_svc: rti;
rti;
rti;
rti;
// 0x5C - Vector address for External Port Buffer 0 (DMA Channel 13)
EP3I_svc: rti;
rti;
rti;
rti;
// 0x60 - Vector address for Link service request:
LSRQ_svc: rti;
rti;
rti;
rti;
// 0x64 - Vector address for DAG1 buffer 7 circular buffer overflow:
CB7I_svc: rti;
rti;
rti;
rti;
// 0x68 - Vector address for DAG2 buffer 15 circular buffer overflow:
CB15I_svc: rti;
rti;
rti;
rti;
// 0x6C - Vector address for lower priority timer interrupt:
TMZLI_svc: rti;
rti;
rti;
rti;
// 0x70 - Vector address for fixed-point overflow interrupt:
FIXI_svc: rti;
rti;
rti;
rti;
// 0x74 - Vector address for floating-point overflow exception interrupt:
FLTOI_svc: rti;
rti;
rti;
rti;
// 0x78 - Vector address for floating-point underflow exception interrupt:
FLTUI_svc: rti;
rti;
rti;
rti;
// 0x7C - Vector address for floating-point invalid exception interrupt:
FLTII_svc: rti;
rti;
rti;
rti;
// 0x80 - Vector address for user software interrupt 0:
SFT0I_svc: rti;
rti;
rti;
rti;
// 0x84 - Vector address for user software interrupt 1:
SFT1I_svc: rti;
rti;
rti;
rti;
// 0x88 - Vector address for user software interrupt 2:
SFT2I_svc: rti;
rti;
rti;
rti;
// 0x8C - Vector address for user software interrupt 3:
SFT3I_svc: rti;
rti;
rti;
rti;
// 0x90 - Reserved Interrupt
reserved_0x90: rti; rti; rti; rti;
.endseg;
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