📄 fir_cplx_blk_test.asm
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/**************************************************************
File Name: fir_cplx_blk_test.asm
Date Modified: 2/17/99 RFG
Purpose: Program to call fir_cplx_blk.asm
**************************************************************/
#include "def21160.h"
#define TAPS 8
#define N 48
.extern fir_cplx_blk;
/* DM data */
.section/dm seg_dmda;
.ALIGN 2;
.var DELAYLINE[2*TAPS];
.ALIGN 2;
.var INPUT[2*N] = "input.dat";
/* PM long-word data */
.section/dm seg_pm64;
.ALIGN 2;
.var OUTPUT[2*N+2]; /* the extra word at the beginning of the */
/* output buffer allows an optimization in the outer */
/* loop of the kernel -- the write of the previously */
/* computed real/imag output samples is done at the */
/* top of the outer loop rather than at the bottom. */
/* this allows a dual parallel move and saves 1 cycle */
/* PM data */
.section/dm seg_pmda;
.ALIGN 2;
.var COEFADR[2*TAPS] = "cfircoeffs.dat";
/* PM interrupt vector code */
.section/pm seg_rth;
Reserved_1: rti; nop; nop; nop;
Chip_Reset: idle; jump start; nop; nop;
/* program memory code */
.section/pm seg_pmco;
/* Initialization code */
start:
b0 = DELAYLINE;
l0 = @DELAYLINE;
r0 = b0;
r0 = lshift r0 by -1;
b1 = r0; /* Set a pointer to the DELAYLINE in Long-word space */
l1 = @DELAYLINE/2; /* to do a dual data, SIMD, Long-word access. */
b6 = INPUT;
l6=0;
b8 = COEFADR;
l8 = @COEFADR;
b9 = OUTPUT;
l9 = @OUTPUT;
m1 = 2;
m3 = -1;
m4 = -2;
m9 = 2;
m10 = 1;
r1 = TAPS;
call fir_cplx_blk (db);
r2 = N;
r3 = TAPS-2;
/* Terminate and wait */
wait1: jump wait1;
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