sngks32cend.h

vxworks bsp for 4510 in tornato 2.2

union UNION_MACCON
    {
        struct MACCON_PACKED    macCon_reg;
        UINT32 macCon_resetval;
    }__attribute__((__packed__));
typedef union UNION_MACCON MACCON;



#if (_BYTE_ORDER == _LITTLE_ENDIAN)
struct CAMCON_PACKED
    {
    UINT32 stationAccept:1;
    UINT32 groupAccept:1;
    UINT32 broadcastAccept:1;
    UINT32 negCam:1;
    UINT32 cmpEnable:1;
    UINT32 reserved_0:27;
    }__attribute__((__packed__));
#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/
struct CAMCON_PACKED
    {
    UINT32 reserved_0:27;
    UINT32 cmpEnable:1;
    UINT32 negCam:1;
    UINT32 broadcastAccept:1;
    UINT32 groupAccept:1;
    UINT32 stationAccept:1;
    }__attribute__((__packed__));
#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/
union UNION_CAMCON
    {
        struct CAMCON_PACKED    camCon_reg;
        UINT32 camCon_resetval;
    }__attribute__((__packed__));
typedef union UNION_CAMCON CAMCON;


#if (_BYTE_ORDER == _LITTLE_ENDIAN)
struct MACTXCON_PACKED
    {
    UINT32 transmitEnable:1;
    UINT32 transmitHaltReq:1;
    UINT32 suppressPadding:1;
    UINT32 suppressCRC:1;
    UINT32 fastBackOff:1;
    UINT32 noDefer:1;
    UINT32 sendPause:1;
    UINT32 sqeTestModeEnable:1;
    UINT32 enableUnderRun:1;
    UINT32 enableDeferral:1;
    UINT32 enableNoCarrier:1;
    UINT32 enableExcessCollision:1;
    UINT32 enableLateCollison:1;
    UINT32 enableTxParity:1;
    UINT32 enableCompletion:1;
    UINT32 reserved_0:17;
    }__attribute__((__packed__));
#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/
struct MACTXCON_PACKED
    {
    UINT32 reserved_0:17;
    UINT32 enableCompletion:1;
    UINT32 enableTxParity:1;
    UINT32 enableLateCollison:1;
    UINT32 enableExcessCollision:1;
    UINT32 enableNoCarrier:1;
    UINT32 enableDeferral:1;
    UINT32 enableUnderRun:1;
    UINT32 sqeTestModeEnable:1;
    UINT32 sendPause:1;
    UINT32 noDefer:1;
    UINT32 fastBackOff:1;
    UINT32 suppressCRC:1;
    UINT32 suppressPadding:1;
    UINT32 transmitHaltReq:1;
    UINT32 transmitEnable:1;
    }__attribute__((__packed__));
#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/
union UNION_MACTXCON
    {
        struct MACTXCON_PACKED    macTxCon_reg;
        UINT32 macTxCon_resetval;
    }__attribute__((__packed__));
typedef union UNION_MACTXCON MACTXCON;



#if (_BYTE_ORDER == _LITTLE_ENDIAN)
struct MACTXSTAT_PACKED
    {
    UINT32 transmitCollCount:4;
    UINT32 excessiveCollision:1;
    UINT32 transmitDeferred:1;
    UINT32 paused:1;
    UINT32 intrOnTransmit:1;
    UINT32 underRun:1;
    UINT32 deferral:1;
    UINT32 noCarrier:1;
    UINT32 sqe:1;
    UINT32 lateCollision:1;
    UINT32 transmitParityError:1;
    UINT32 completion:1;
    UINT32 transmissionHalted:1;
    UINT32 reserved_0:16;
    }__attribute__((__packed__));
#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/
struct MACTXSTAT_PACKED
    {
    UINT32 reserved_0:16;
    UINT32 transmissionHalted:1;
    UINT32 completion:1;
    UINT32 transmitParityError:1;
    UINT32 lateCollision:1;
    UINT32 sqe:1;
    UINT32 noCarrier:1;
    UINT32 deferral:1;
    UINT32 underRun:1;
    UINT32 intrOnTransmit:1;
    UINT32 paused:1;
    UINT32 transmitDeferred:1;
    UINT32 excessiveCollision:1;
    UINT32 transmitCollCount:4;
    }__attribute__((__packed__));
#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/
union UNION_MACTXSTAT
    {
        struct MACTXSTAT_PACKED    macTxStat_reg;
        UINT32 macTxStat_resetval;
    }__attribute__((__packed__));
typedef union UNION_MACTXSTAT MACTXSTAT;


#if (_BYTE_ORDER == _LITTLE_ENDIAN)
struct MACRXCON_PACKED
    {
    UINT32 receiveEnable:1;
    UINT32 receiveHaltReq:1;
    UINT32 longEnable:1;
    UINT32 shortEnable:1;
    UINT32 stripCRCVal:1;
    UINT32 passCtrlPacket:1;
    UINT32 ignoreCRCValue:1;
    UINT32 reserved_0:1;
    UINT32 enableAlignment:1;
    UINT32 enableCRCError:1;
    UINT32 enableOverFlow:1;
    UINT32 enableLongError:1;
    UINT32 reserved_1:1;
    UINT32 enableReceiveParity:1;
    UINT32 enableGood:1;
    UINT32 reserved_2:17;
    }__attribute__((__packed__));
#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/
struct MACRXCON_PACKED
    {
    UINT32 reserved_2:17;
    UINT32 enableGood:1;
    UINT32 enableReceiveParity:1;
    UINT32 reserved_1:1;
    UINT32 enableLongError:1;
    UINT32 enableOverFlow:1;
    UINT32 enableCRCError:1;
    UINT32 enableAlignment:1;
    UINT32 reserved_0:1;
    UINT32 ignoreCRCValue:1;
    UINT32 passCtrlPacket:1;
    UINT32 stripCRCVal:1;
    UINT32 shortEnable:1;
    UINT32 longEnable:1;
    UINT32 receiveHaltReq:1;
    UINT32 receiveEnable:1;
    }__attribute__((__packed__));
#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/

union UNION_MACRXCON
    {
        struct MACRXCON_PACKED    macRxCon_reg;
        UINT32 macRxCon_resetval;
    }__attribute__((__packed__));
typedef union UNION_MACRXCON MACRXCON;


#if (_BYTE_ORDER == _LITTLE_ENDIAN)
struct MACRXSTAT_PACKED
    {
    UINT32 reserved_0:5;
    UINT32 ctrlFrameReceived:1;
    UINT32 intrOnReceive:1;
    UINT32 receive10MbStatus:1;
    UINT32 alignmentError:1;
    UINT32 crcError:1;
    UINT32 overflowError:1;
    UINT32 longError:1;
    UINT32 reserved_1:1;
    UINT32 receiveParityError:1;
    UINT32 goodReceived:1;
    UINT32 receptionHalted:1;
    UINT32 reserved_2:16;
    }__attribute__((__packed__));
#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/
struct MACRXSTAT_PACKED
    {
    UINT32 reserved_2:16;
    UINT32 receptionHalted:1;
    UINT32 goodReceived:1;
    UINT32 receiveParityError:1;
    UINT32 reserved_1:1;
    UINT32 longError:1;
    UINT32 overflowError:1;
    UINT32 crcError:1;
    UINT32 alignmentError:1;
    UINT32 receive10MbStatus:1;
    UINT32 intrOnReceive:1;
    UINT32 ctrlFrameReceived:1;
    UINT32 reserved_0:5;
    }__attribute__((__packed__));
#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/

union UNION_MACRXSTAT
    {
        struct MACRXSTAT_PACKED    macRxCon_reg;
        UINT32 macRxCon_resetval;
    }__attribute__((__packed__));

typedef union UNION_MACRXSTAT MACRXSTAT;


#if (_BYTE_ORDER == _LITTLE_ENDIAN)
struct STACON_PACKED
    {
    UINT32 phyRegisterAddr:5;
    UINT32 phyAddr:5;
    UINT32 write:1;
    UINT32 busy:1;
    UINT32 preambleSuppress:1;
    UINT32 mdc_Clockrating:3;
    UINT32 reserved_0:16;
    }__attribute__((__packed__));
#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/
struct STACON_PACKED
    {
    UINT32 reserved_0:16;
    UINT32 mdc_Clockrating:3;
    UINT32 preambleSuppress:1;
    UINT32 busy:1;
    UINT32 write:1;
    UINT32 phyAddr:5;
    UINT32 phyRegisterAddr:5;
    }__attribute__((__packed__));
#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/
union UNION_STACON
    {
        struct STACON_PACKED    staCon_reg;
        UINT32 staCon_resetval;
    }__attribute__((__packed__));
typedef union UNION_STACON STACON;


#if (_BYTE_ORDER == _LITTLE_ENDIAN)
struct CAMEN_PACKED
    {
    UINT32 camEnable:21;
    UINT32 reserved_0:11;
    }__attribute__((__packed__));
#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/
struct CAMEN_PACKED
    {
    UINT32 reserved_0:11;
    UINT32 camEnable:21;
    }__attribute__((__packed__));
#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/
union UNION_CAMEN
    {
        struct CAMEN_PACKED    camen_reg;
        UINT32 camen_resetval;
    }__attribute__((__packed__));
typedef union UNION_CAMEN CAMEN;


#if (_BYTE_ORDER == _LITTLE_ENDIAN)
struct EMISSCNT_PACKED
    {
    UINT32 alignmentErrorCount:16;
    UINT32 reserved_0:16;
    }__attribute__((__packed__));
#else /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/
struct EMISSCNT_PACKED
    {
    UINT32 reserved_0:16;
    UINT32 alignmentErrorCount:16;
    }__attribute__((__packed__));
#endif /*(_BYTE_ORDER == _LITTLE_ENDIAN)*/
union UNION_EMISSCNT
    {
    struct EMISSCNT_PACKED    emisscnt_reg;
    UINT32 emisscnt_resetval;
    }__attribute__((__packed__));
typedef union UNION_EMISSCNT EMISSCNT;

typedef struct etherStatistics
{
    /* Receive statistics counters from */
    UINT32 rxGood;
    UINT32 rxBad;
    UINT32 rxOvMaxSize;
    UINT32 rxCtlRecd;
    UINT32 rx10Stat;
    UINT32 rxAlignErr;
    UINT32 rxCRCErr;
    UINT32 rxOverflowErr;
    UINT32 rxLongErr;
    UINT32 rxParErr;
    UINT32 rxHalted;
    /* Transmit statistics counters */
    UINT32 txGood;
    UINT32 txUnderErr;
    UINT32 txExCollErr;
    UINT32 txDeferredErr;
    UINT32 txPaused;
    UINT32 txDeferErr;
    UINT32 txNCarrErr;
    UINT32 txSQE;
    UINT32 txLateCollErr;
    UINT32 txParErr;
    UINT32 txHalted;
} ETHER_STATISTICS;

/**********BDMA control registers **************/

#define SNGKS32C_BDMATXCON         (ASIC_BASE+0x9000)
#define SNGKS32C_BDMARXCON         (ASIC_BASE+0x9004)
#define SNGKS32C_BDMATXPTR         (ASIC_BASE+0x9008)
#define SNGKS32C_BDMARXPTR         (ASIC_BASE+0x900C)
#define SNGKS32C_BDMARXLSZ         (ASIC_BASE+0x9010)
#define SNGKS32C_BDMASTAT        (ASIC_BASE+0x9014)

/****** Content Addressable Memory  registers ******/
#define SNGKS32C_CAM_BASE    (ASIC_BASE+0x9100)
#define SNGKS32C_CAM0    (ASIC_BASE+0x9100)
#define SNGKS32C_CAM1     (ASIC_BASE+0x9106)
#define SNGKS32C_CAM2     (ASIC_BASE+0x910C)
#define SNGKS32C_CAM3    (ASIC_BASE+0x9112)
#define SNGKS32C_CAM4     (ASIC_BASE+0x9118)
#define SNGKS32C_CAM5     (ASIC_BASE+0x911e)
#define SNGKS32C_CAM6     (ASIC_BASE+0x9124)
#define SNGKS32C_CAM7     (ASIC_BASE+0x912a)
#define SNGKS32C_CAM8     (ASIC_BASE+0x9130)
#define SNGKS32C_CAM9     (ASIC_BASE+0x9136)
#define SNGKS32C_CAM10     (ASIC_BASE+0x913c)
#define SNGKS32C_CAM11     (ASIC_BASE+0x9142)
#define SNGKS32C_CAM12    (ASIC_BASE+0x9148)
#define SNGKS32C_CAM13    (ASIC_BASE+0x914e)
#define SNGKS32C_CAM14     (ASIC_BASE+0x9154)
#define SNGKS32C_CAM15     (ASIC_BASE+0x915a)
#define SNGKS32C_CAM16     (ASIC_BASE+0x9160)
#define SNGKS32C_CAM17     (ASIC_BASE+0x9166)
#define SNGKS32C_CAM18     (ASIC_BASE+0x916c)
#define SNGKS32C_CAM19     (ASIC_BASE+0x9172)
#define SNGKS32C_CAM20     (ASIC_BASE+0x9178)

/*******Buffer registers for debug pupose ***/

    /* to be removed after driver development */
#define SNGKS32C_BDMATXBUF     (ASIC_BASE+0x9200)
#define SNGKS32C_BDMARXBUF    (ASIC_BASE+0x9800)

/***********MAC control registers**************/

#define SNGKS32C_MACCON             (ASIC_BASE+0xA000)
#define SNGKS32C_CAMCON             (ASIC_BASE+0xA004)
#define SNGKS32C_MACTXCON           (ASIC_BASE+0xA008)
#define SNGKS32C_MACTXSTAT          (ASIC_BASE+0xA00C)
#define SNGKS32C_MACRXCON           (ASIC_BASE+0xA010)
#define SNGKS32C_MACRXSTAT          (ASIC_BASE+0xA014)
#define SNGKS32C_STADATA            (ASIC_BASE+0xA018)
#define SNGKS32C_STACON             (ASIC_BASE+0xA01C)
#define SNGKS32C_CAMEN              (ASIC_BASE+0xA028)
#define SNGKS32C_EMISSCNT           (ASIC_BASE+0xA03C)
#define SNGKS32C_EPZCNT             (ASIC_BASE+0xA040)
#define SNGKS32C_ERMPZCNT           (ASIC_BASE+0xA044)
#define SNGKS32C_ETXSTAT            (ASIC_BASE+0x9040)

/* interrupt levels */
#define SNGKS32C_INT_LVL_BDMATx        16    /* BDMA Tx Interrupt */
#define SNGKS32C_INT_LVL_BDMARx        17    /* BDMA Rx Interrupt */
#define SNGKS32C_INT_LVL_MACTx         18    /* MAC Tx Interrupt*/
#define SNGKS32C_INT_LVL_MACRx         19    /* MAC Rx Interrupt */


/* Configuration items */
#define SNGKS32CEND_DEV_NAME       "sng"
#define SNGKS32CEND_DEV_NAME_LEN   4
#define ENET_HDR_REAL_SIZ          14
#define SNGKS32C_END_ALIGN         0
#define END_BUFSIZ     (ETHERMTU + ENET_HDR_REAL_SIZ + 6 + SNGKS32C_END_ALIGN)

/* The definition of the driver control structure */

typedef struct end_device
    {
    END_OBJ           end;             /* The class we inherit from. */
    int               unit;            /* unit number */
    int               ivecBdmaTx;      /* bdmaTx interrupt vector */
    int               ivecBdmaRx;      /* bdmaRx interrupt vector */
    int               ivecMacTx;       /* macTx  interrupt vector */
    int               ivecMacRx;       /* macRx  interrupt vector */
    long              flags;           /* Our local flags. */
    UCHAR             enetAddr[6];     /* ethernet address */
    CACHE_FUNCS      *cacheFuncs;      /* cache function pointers */
    UCHAR             netSpeed;        /* 10 or 100 */
    UCHAR             duplexMode;      /* HDX = 0. FDX = 1 */
    UCHAR             autoNeg;         /* 1 = autoneg enabled */
    BOOL              fdInitialized;   /* Set to TRUE after FD allocation */
    ETHER_STATISTICS  statistics;      /* Ethernet statistics counters */

   /* Array for storing addresses Max = 21, i.e. 32 long words */
    UINT32            addrList[32];

    UINT32            mcastAddrCount; /* Number of valid multicast addresses */
    BOOL              loaded;          /* interface has been loaded */
    BOOL              rxHandling;
    BOOL              resetting;
    RECEIVE_FRAME_DESC   *pRxFrameDesc;
    TRANSMIT_FRAME_DESC  *pTxFrameDesc;
    END_ERR           lastError;      /* Last error passed to muxError */

    } END_DEVICE;


#ifdef __cplusplus

}
#endif

#endif /* __INCsngks32cEndh */