wrsbcarm7.h

vxworks bsp for 4510 in tornato 2.2

/* sbcarm7.h - WindRiver SBC ARM7 header file */


/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01f,16jul02,m_h  C++ protection
01e,04jan02,m_h  minor cleanup
01d,03dec01,m_h  remove Diab warnings
01c,27sep01,m_h  base MAC address on user DIP setting
01b,22may01,m_h  documentation
01a,12apr01,m_h  created from snds100 template.
*/

/*
This file contains I/O address and related constants for the SBC ARM7 board.
*/

#ifndef    INCsbcarm7h
#define    INCsbcarm7h

#ifdef __cplusplus
extern "C" {
#endif

#include "sngks32c.h"


#define TARGET_SBCARM7


#define SBCARM7_FLASH_BASE 0x1000000


/*
 * Local-to-Bus memory address constants:
 * the local memory address always appears at 0 locally;
 * it is not dual ported.
 */

#define LOCAL_MEM_LOCAL_ADRS  0x00000000    /* fixed */
#define LOCAL_MEM_BUS_ADRS    0x00000000    /* fixed */


#define BUS                   BUS_TYPE_NONE


#define SBCARM7_CPU_SPEED         50000000    /* CPU clocked at 50 MHz. The timer */
                    /* speed is related to this */


/* definitions for the KS32C50100 UART */

#define N_SBCARM7_UART_CHANNELS     2        /* number of SBCARM7 UART chans */
#define N_SIO_CHANNELS          N_SBCARM7_UART_CHANNELS
#define N_UART_CHANNELS         N_SBCARM7_UART_CHANNELS
#define UART_REG_ADDR_INTERVAL  1        /* registers 4 bytes apart */


/* LED Registers (write) */
#define  SBCARM7_LEDREG             0x3fd4000

/* USER DIP switch (read) */
#define  SBCARM7_USERREG            0x3fd4000
#define READ_USERDIP()              (*((volatile char *)SBCARM7_USERREG) & 0xff)

/*************************************************************************
 *
 * DRAM Memory Bank 0 area MAP for Exception vector table 
 * and Stack, User code area. 
 *
 */

#define DRAM_BASE           0x0          /* Final start address of DRAM */
#define DRAM_LIMIT          0x400000
#define RESET_DRAM_START    0x1000000    /* Start of DRAM on power-up */
#define RESET_ROM_START     0x0          /* Start of ROM on power-up */

/****************************************************************************
 *
 * Format of the Program Status Register 
 */

#define FBit         0x40
#define IBit         0x80
#define LOCKOUT      0xC0     /* Interrupt lockout value */
#define LOCK_MSK     0xC0     /* Interrupt lockout mask value */
#define MODE_MASK    0x1F     /* Processor Mode Mask */
#define UDF_MODE     0x1B     /* Undefine Mode(UDF) */
#define ABT_MODE     0x17     /* Abort Mode(ABT) */
#define SUP_MODE     0x13     /* Supervisor Mode (SVC) */
#define IRQ_MODE     0x12     /* Interrupt Mode (IRQ) */
#define FIQ_MODE     0x11     /* Fast Interrupt Mode (FIQ) */
#define USR_MODE     0x10     /* User Mode(USR) */

/*************************************************************************
 * SYSTEM CLOCK 
 */

#define MHz            1000000
#define fMCLK_MHz      50000000     /* 50MHz, KS32C50100*/
#define fMCLK          50           /* fMCLK_MHz/MHz */

/*************************************************************************
 * SYSTEM MEMORY CONTROL REGISTER EQU TABLES 
 */

/* SYSCFG Register Value */
#define SYSCONFIG_VAL           0x07ffffa0    /* System Configuration Value, EDO RAM */
#define SYSCONFIG_VAL_SDRAM     0x87ffff90    /* System Configuration Value, SDRAM */

/* CLKCON Clock configuration register Values */
#define tCDIV           (0<<0)
#define tWE             (0<<16)
#define tMUX            (0<<17)
#define tAC             (0<<18)
#define tTEST           (0<<31)


#define rCLKCON    (tCDIV+tWE+tMUX+tAC+tTEST)

/* EXTACONx External I/O access timing register Values */
#define tCOS0           (1<<0)
#define tACS0           (1<<3)
#define tCOH0           (1<<6)
#define tACC0           (1<<9)
#define tCOS1           (1<<16)
#define tACS1           (1<<19)
#define tCOH1           (1<<22)
#define tACC1           (1<<25)

#define rEXTACON0    (tCOS0+tACS0+tCOH0+tACC0+tCOS1+tACS1+tCOH1+tACC1)

#define tCOS2           (7<<0)
#define tACS2           (7<<3)
#define tCOH2           (7<<6)
#define tACC2           (7<<9)
#define tCOS3           (7<<16)
#define tACS3           (7<<19)
#define tCOH3           (7<<22)
#define tACC3           (7<<25)

#define rEXTACON1    (tCOS2+tACS2+tCOH2+tACC2+tCOS3+tACS3+tCOH3+tACC3)

/***********************************************************
 *
 * -> EXTDBWTH : Memory Bus Width register
 */
#define DSR0  (2<<0)     /* ROM0, 0 : Disable, 1 : Byte etc.*/
#define DSR1  (0<<2)     /* ROM1  */
#define DSR2  (0<<4)     /* ROM2  */
#define DSR3  (0<<6)     /* ROM3  */
#define DSR4  (0<<8)     /* ROM4  */
#define DSR5  (0<<10)    /* ROM5  */
#define DSD0  (2<<12)    /* DRAM0 */
#define DSD1  (0<<14)    /* DRAM1 */
#define DSD2  (0<<16)    /* DRAM2 */
#define DSD3  (0<<18)    /* DRAM3 */
#define DSX0  (1<<20)    /* EXTIO0*/
#define DSX1  (2<<22)    /* EXTIO1*/
#define DSX2  (2<<24)    /* EXTIO2*/
#define DSX3  (1<<26)    /* EXTIO3*/

#define rEXTDBWTH     (DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3)

/***********************************************************
 *
 * -> ROMCON0 : ROM Bank0 Control register 
 */

#define ROMBasePtr0     (0x0<<10)                      /*=0x00000000*/
#define ROMBasePtr0_S   (0x100<<10)                    /*=0x01000000*/
#define ROMEndPtr0      ((ROM_SIZE>>16)<<20)           /*=0x00200000*/
#define ROMEndPtr0_S    (((ROM_SIZE>>16)+0x100)<<20)   /*=0x01200000*/
#define PMC0            0x0             /* 0x0=Normal ROM, 0x1=4Word Page etc.*/
#define rTpa0           (0x0<<2)        /* 0x0=5Cycle, 0x1=2Cycle etc.*/
#define rTacc0          (0x6<<4)        /* 0x0=Disable, 0x1=2Cycle etc.*/
#define rROMCON0        (ROMEndPtr0+ROMBasePtr0+rTacc0+rTpa0+PMC0)
#define rROMCON0_S      (ROMEndPtr0_S+ROMBasePtr0_S+rTacc0+rTpa0+PMC0)

/***************************************************************************
 * -> ROMCON1 : ROM Bank1 Control register, Mailbox Interface
 */

#define ROMBasePtr1     (0x3fc<<10)                 /*=0x0fc0000*/
#define ROMEndPtr1      ((0xfd0000>>12)<<20)        /*=0x0fd0000*/
#define PMC1            0x0             /* 0x0=Normal ROM, 0x1=4Word Page etc.*/
#define rTpa1           (0x0<<2)        /* 0x0=5Cycle, 0x1=2Cycle etc.*/
#define rTacc1          (0x6<<4)        /* 0x0=Disable, 0x1=2Cycle etc.*/
#define rROMCON1        (ROMEndPtr1+ROMBasePtr1+rTacc1+rTpa1+PMC1)

/***************************************************************************
 * -> ROMCON2 : ROM Bank2 Control register, EEPROM
 */

#define ROMBasePtr2     (0x3fb<<10)                 /*=0x0fb0000*/
#define ROMEndPtr2      ((0xfc0000>>12)<<20)       /*=0x0fc0000*/
#define PMC2            0x0             /* 0x0=Normal ROM, 0x1=4Word Page etc.*/
#define rTpa2           (0x0<<2)        /* 0x0=5Cycle, 0x1=2Cycle etc.*/
#define rTacc2          (0x6<<4)        /* 0x0=Disable, 0x1=2Cycle etc.*/
#define rROMCON2        (ROMEndPtr2+ROMBasePtr2+rTacc2+rTpa2+PMC2)

/***************************************************************************
 * -> ROMCONx : unused ROM Bank Control registers
 */

#define rROMCON3      0x60
#define rROMCON4      0x60
#define rROMCON5      0x60        /*ROMEndPtr5+ROMBasePtr5+rTacc5+rTpa5+PMC5*/

/****************************************************************************
 * -> DRAMCON0 : RAM Bank0 control register  (EDO)
 */
#define EDO_Mode0          1             /*(EDO)0=Normal, 1=EDO DRAM*/