📄 div32a.asm
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; File Name Div32a.asm"
; Support Email Per@hum.au.dk
; Target MCU AT90Sxxxx
; R e v i s i o n H I S T O R Y
; rev. date who why
; ---- ------------ --- ---------------------------------------------------
; 0.01 May 17, 2001 PB Creation after a great idea from Thorleif Bundgaard
;
;.DEVICE AT90S4414 ; change if an other device is used
;.include "4414def.inc" ; change if an other device is used
.def Divisor =r8
.def Divisor1 =r9
.def Base =r10
.def Base1 =r11
.def Base2 =r12
.def Base3 =r13
.def Temp =r16
.def Lcount =r18
; ********** MAX 32 bit value = Result (Int * Divisor) + Fraction **********
; If you do not obey this you'll get overflow and uncertain results !!!!
; This means if the divisor can't be garantied to be more than 1
; then the biggest Base input IS $0000FFFFh + $0000h = $0000FFFFh
; Entry : Base3, Base2, Base1, Base / Divisor1, Divisor
; Result :
; Int : Base1, Base
; Fraction : Base3, Base2
; 24 Words off program space
; Execution at 1 MHz. between 220 and 250 uS. depending on the input numbers
Div32a: rcall Div1
Div1: ldi Lcount,8
mov Temp,Base1 ; Only because we can't do "sbr" to regs below r16
mov Base1,Base
Div2: add Temp,Temp ; Shift 24 bit register one bit left
adc Base2,Base2
adc Base3,Base3
brcs Div5 ; skip if overflow
sub Base2,Divisor ; Subtract divisor
sbc Base3,Divisor1
brcc Div3 ; Skip if ok
add Base2,Divisor ; Else restore
adc Base3,Divisor1
dec Temp
Div3: inc Temp
Div4: dec Lcount ; Finished ?
brne Div2 ; No, Loopback
mov Base,Temp ; Reorder registers to correct order
ret
Div5: ori Temp,$01 ; Move carry to last bit of base
sub Base2,Divisor ; Subtract divisor
sbc Base3,Divisor1
rjmp Div4
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