make.txt

tasm source document descript

			Makefile	Command line
			--------	------------
Spaces allowed before
and after =		Yes		No

Space allowed before
macroName		No		Yes


Using a macro
-------------
To use a macro in a makefile, type "$(MacroName)" where MacroName is the
name of a defined macro. You can use braces {} and parentheses () to

MAKE expands macros at various times depending on where they appear in
the makefile:

  o  Nested macros are expanded when the outer macro is invoked.

  o  Macros in rules and directives are expanded when MAKE first looks at
     the makefile.

  o  Macros in commands are expanded when the command is executed.


String substitutions in macros
------------------------------
MAKE lets you temporarily substitute characters in a previously
defined macro.  For example, if you defined a macro called SOURCE as
"SOURCE = f1.cpp f2.cpp f3.cpp", you could substitute the characters
.OBJ for the characters .CPP by using "$(SOURCE:.CPP=.OBJ)". The
substitution doesn't redefine the macro.

Rules for macro substitution:

  o  Syntax: $(MacroName:original_text=new_text)

  o  No whitespace before or after the colon.

  o  Characters in "original_text" must exactly match the characters in the
     macro definition; this text is case-sensitive.

MAKE now lets you use macros within substitution macros. For example:

  MYEXT=.C
  SOURCE=f1.cpp f2.cpp f3.cpp
  $(SOURCE:.cpp=$(MYEXT))         #Changes f1.cpp to f1.C, etc.


Default MAKE macros
-------------------
MAKE contains several default macros you can use in your makefiles.
The following table lists the macro definition and what it expands to
in explicit and implicit rules.

Macro	Expands in implicit:	Expands in explicit:	Example
-----	--------------------	--------------------	-------
$*	path\dependent file	path\target file	C:\PROJ\MYTARGET

$<	path\dependent file+ext	path\target file+ext	C:\PROJ\MYTARGET.OBJ

$:	path for dependents	path for target		C:\PROJ

$.	dependent file+ext	target file + ext	MYSOURCE.C

$&	dependent file   	target file     	MYSOURCE

$@	path\target file+ext	path\target file+ext	C:\PROJ\MYSOURCE.C

$**	path\dependent file+ext	all dependents file+ext	F1.CPP F2.CPP F3.CPP

$?	path\dependent file+ext	old dependents		FILE1.CPP


Macro		Expands to:	Comment
-----		-----------	-------
__MSDOS__	1		If running under DOS.

__MAKE__	0x0370		MAKE's hex version number.

MAKE		make		MAKE's executable file name.

MAKEFLAGS	options		The options typed at the
				command line.

MAKEDIR		directory	Directory where MAKE.EXE is
				located.


Modifying default macros
------------------------
When the default macros listed in the preceding table doesn't give you
the exact string you want, macro modifiers let you extract parts of
the string to suit your purpose.

To modify a default macro, use this syntax:

	$(MacroName [modifier])

The following table lists macro modifiers and provides examples of
their use.

Modifier	Part of file name expanded	Example	Result
--------	--------------------------	--------------
D		Drive and directory		$(<D)	C:\PROJECTA\

F		Base and extension		$(<F)	MYSOURCE.C

B		Base only			$(<B)	MYSOURCE

R		Drive, directory, and base	$(<R)	C:\PROJECTA\MYSOURCE


Using MAKE directives
=====================
MAKE directives resemble directives in languages such as C and Pascal,
and perform various control functions, such as displaying commands
onscreen before executing them. MAKE directives begin either with an
exclamation point or a period. The following table lists MAKE directives
and their corresponding command-line options (directives override
command-line options). Each directive is described in more detail
following the table.

Directive	Option		Description
---------	------		-----------
.autodepend	-a		Turns on autodependency checking.

!elif				Acts like a C "else if".

!else				Acts like a C "else".

!endif				Ends an "!if", "!ifdef", or "!ifndef"
				statement.

!error				Stops MAKE and prints an error message.

!if				Begins a conditional statement.

!ifdef				If defined that acts like a C "ifdef", but
				with macros rather than "#define" directives.

!ifndef				If not defined.

.ignore		-i		MAKE ignores the return value of a command.

!include			Specifies a file to include in the makefile.

!message			Lets you print a message from a makefile.

.noautodepend	-a-		Turns off autodependency checking.

.noIgnore	-i-		Turns off ".Ignore".

.nosilent	-s-		Displays commands before MAKE executes them.

.noswap		-S-		Tells MAKE not to swap itself out of memory
				before executing a command.

.path.ext			Tells MAKE to search for files with the
				extension .ext in path directories.

.precious			Saves the target or targets even if the
				build fails.

.silent		-s		Executes without printing the commands.

.suffixes			Determines the implicit rule for ambiguous
				dependencies.

.swap		-S		Tells MAKE to swap itself out of memory
				before executing a command.

!undef				Clears the definition of a macro.


.autodepend
-----------
Autodependencies occur in .OBJ files that have corresponding .CPP, .C,
or .ASM files. With ".autodepend" on, MAKE compares the dates and times
of all the files used to build the .OBJ. If the dates and times of the
files used to build the .OBJ are different from the date-time stamp of
the.OBJ file, the .OBJ file is recompiled. You can use ".autodepend" or
-a in place of linked dependencies.


!error
------
This is the syntax of the !error directive:

  !error message

MAKE stops processing and prints the following string when it
encounters this directive:

  Fatal makefile exit code: Error directive: message

Embed !error in conditional statements to abort processing and print
an error message, as shown in the following example:

  !if !$d(MYMACRO)
  #if MYMACRO isn't defined
  !error MYMACRO isn't defined
  !endif

If MYMACRO in the example isn't defined, MAKE prints the following
message:

  Fatal makefile 4: Error directive: MYMACRO isn't defined


Summing up error-checking controls
- - - - - - - - - - - - - - - - - -
Four different controls turn off error checking:

  o  The .ignore directive turns off error checking for a selected portion
     of the makefile.

  o  The -i command-line option turns off error checking for the entire
     makefile.

  o  The -num command operator, which is entered as part of a rule, turns
     off error checking for the related command if the exit code exceeds
     the specified number.

  o  The - command operator turns off error checking for the related
     command regardless of the exit code.


!if and other conditional directives
------------------------------------
The !if directive works like C if statements. The syntax of !if and the
other conditional directives resembles compiler conditionals.


!include
--------
This directive is like the #include preprocessor directive for the C
or C++ language--it lets you include the text of another file in the
makefile:

  !include <filename>

You can enclose <filename> in quotation marks ("") or angle brackets
(<>) and nest directives to unlimited depth, but writing duplicate
!include directives in a makefile isn't permitted--you'll get the
error message "cycle in the include file".

Rules, commands, or directives must be complete within a single source
file; you can't start a command in an !include file, then finish it in
the makefile.

MAKE searches for !include files in the current directory unless
you've specified another directory with the -I option.


!message
--------
The !message directive lets you send messages to the screen from a
makefile. You can use these messages to help debug a makefile that
isn't working the way you'd like it to. For example, if you're having
trouble with a macro definition, you could put this line in your
makefile:

  !message The macro is defined here as: $(<MacroName>)

When MAKE interprets this line, it will print onscreen "The macro is
defined here as: .CPP", if the macro expands to .CPP at that line.
Using a series of !message directives, you can debug your makefiles.


.path.ext
---------
The .path.ext directive tells MAKE where to look for files with a
certain extension. The following example tells MAKE to look for files
with the .c extension in C:\SOURCE or C:\CFILES and to look for files
with the .obj extension in C:\OBJS.

  .path.c = C:\CSOURCE;C:\CFILES
  .path.obj = C:\OBJS


.precious
---------
If a MAKE build fails, MAKE deletes the target file. The .precious
directive prevents the file deletion, which is desired for certain
kinds of targets such as libraries. When a build fails to add a module
to a library, you don't want the library to be deleted.

The syntax for .precious is:

  .precious: target [target] . . . [target]


.suffixes
---------
The .suffixes directive tells MAKE the order (by file extensions) for
building implicit rules.

The syntax of the .suffixes directive is:

  .suffixes: .ext [.ext]  [.ext] . . . [.ext]

.ext represents the dependent file extension in implicit rules. For
example, you could include the line ".suffixes: .asm .c .cpp" to tell
MAKE to interpret implicit rules beginning with the ones dependent on
.ASM files, then .C files, then .CPP files, regardless of what order
they appear in the makefile.

The following example shows a makefile containing a .suffixes
directive that tells MAKE to look for a source file (MYPROG.EXE) first
with an .ASM extension, next with a .C extension, and finally with a
.CPP extension. If MAKE finds MYPROG.ASM, it builds MYPROG.OBJ from
the assembler file by calling TASM. MAKE then calls TLINK; otherwise,
MAKE searches for MYPROG.C to build the .OBJ file, and so on.

  .suffixes: .asm .c .cpp

  myprog.exe: myprog.obj
  tlink myprog.obj

  .cpp.obj:
	bcc -P $<
  .asm.obj:
	tasm /mx $<
  .c.obj:
	bcc -P- $<


!undef
------
The syntax of the !undef directive is:

  !undef MacroName

!undef (undefine) clears the given macro, MacroName, causing an !ifdef
MacroName test to fail.


Using macros in directives
--------------------------
The macro $d is used with the !if conditional directive to perform
some processing if a specific macro is defined. The $d is followed by
a macro name, enclosed in parentheses or braces, as shown in the
following example.

  !if $d(DEBUG)                #If DEBUG is defined,
  bcc -v f1.cpp f2.cpp         #compile with debug information;
  !else                        #otherwise (else)
  bcc -v- f1.cpp f2.cpp        #don't include debug information.
  !endif

Don't use the $d macro when MAKE is invoked with the -N option.

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