dj-18.asm

单片机音频信号处理软件2.

.include  "1200def.inc"

;***** Global Registers

.def	x_sr		=r0	;
.def	x_o_buf_l	=r1	;codec output buffer register
.def	x_o_buf_h	=r2
.def	x_i_buf_l	=r3	;codec input buffer register
.def	x_i_buf_h	=r4
.def	x_adc_com	=r5
.def	x_adc_value	=r6

.def	x_o_data_l	=r7	;codec output data register
.def	x_o_data_h	=r8
.def	x_delay_l	=r9	;adc delay value
.def	x_delay_h	=r10
.def	x_portd_i_buf	=r11

.def	x_adc_del	=r12
.def	x_adc_rep	=r13
.def	x_00		=r14
.def	x_80		=r15


.def	u_tmp		=r16
.def	u_tmp_l		=r17
.def	u_tmp_h		=r18
.def	u_adc_pin	=r19
.def	u_i_data_l	=r20	;codec input data register
.def	u_i_data_h	=r21			=r20
.def	u_adc_clk_cunt	=r22
.def	u_rep_val	=r23
.def	u_fb_data_l	=r24
.def	u_fb_data_h	=r25
.def	u_o_ptr_l	=r26
.def	u_o_ptr_h	=r27
.def	u_i_ptr_l	=r28
.def	u_i_ptr_h	=r29
.def	u_flags		=r30
.def	u_portd_o_buf	=r31



;***** Constant


.equ	codec_do	= 0

.equ	codec_bck	= 2
.equ	codec_fs	= 3
.equ	adc_ch0		= 3
.equ	adc_ch1		= 7
.equ	adc_dat_rdy_f	= 2
.equ	k_adc_dat_rdy_f	= 0b00000100
.equ	adc_rec_act_f	= 1
.equ	k_adc_rec_act_f	= 0b00000010	
.equ	adc_di		= 0
.equ	k_adc_di	= 0b00000001
.equ	adc_clk		= 1
.equ	k_adc_clk_pin	= 0b00000010
.equ	k_adc_cs_pin	= 0b00000100
.equ	adc_cs		= 2
.equ	adc_do		= 3
.equ	last_adc_data_clk 	= 13
.equ	last_adc_com_clk	= 5
.equ	by_pass_mode = 0b01010110
.equ	delay_dat_f	= 3
.equ	k_delay_dat_f	= 0b00001000
.equ	enable_effect_f	= 4
.equ	k_toggle_sw	= 0b00010000
.equ	led_pin		= 4
.equ	k_led_pin	= 0b00010000

.equ	adc_sw_dir		= 0b11010111
.equ	sw_pin		= 5
.equ	sw_pressed_f	= 5
.equ	k_sw_pressed_f	= 0b00100000
.equ	effect_latch	= 7
.equ	k_effect_latch	= 0b10000000
.equ	bypass_latch	= 6
.equ	k_bypass_latch	= 0b01000000

	

;flags define
;	forward & reverse effect mode 	0
;	adc receives data ready flag	1
;	adc data ready flag		2
;	delay data process flag		3
;	enable effect state flag 	4
;	switch has pressed flag		5
;	detect switch press		6


.MACRO	latch_all
	;cbi	PORTD,4
	;cbi	PORTD,5
	;cbi	PORTD,6
	;andi	u_portd_o_buf,0b00001111

	ldi	u_portd_o_buf,0b00001111
	out	PORTD,u_portd_o_buf
.ENDMACRO

.MACRO	latch_add_l
;	cbi	PORTD,4
;	sbi	PORTD,5
;	cbi	PORTD,6
;	andi	u_portd_o_buf,0b00001111
;	ori	u_portd_o_buf,0b00101101

	ldi	u_portd_o_buf,0b00101111
	out	PORTD,u_portd_o_buf
.ENDMACRO

.MACRO	latch_add_h
;	sbi	PORTD,4
;	cbi	PORTD,5
;	cbi	PORTD,6

	ldi	u_portd_o_buf,0b00011111
	out	PORTD,u_portd_o_buf
.ENDMACRO

.MACRO	low_ram_read
;	sbi	PORTD,4
;	sbi	PORTD,5
;	cbi	PORTD,6
;	andi	u_portd_o_buf,0b00001111
;	ori	u_portd_o_buf,0b00111101

	ldi	u_portd_o_buf,0b00111111
	out	PORTD,u_portd_o_buf
.ENDMACRO

.MACRO	high_ram_read
;	cbi	PORTD,4
;	cbi	PORTD,5
;	sbi	PORTD,6
;	andi	u_portd_o_buf,0b00001111
;	ori	u_portd_o_buf,0b01001101

	ldi	u_portd_o_buf,0b01001111
	out	PORTD,u_portd_o_buf
.ENDMACRO

.MACRO	low_ram_write
;	sbi	PORTD,4
;	cbi	PORTD,5
;	sbi	PORTD,6
;	andi	u_portd_o_buf,0b00001111
;	ori	u_portd_o_buf,0b01011101

	ldi	u_portd_o_buf,0b01011111
	out	PORTD,u_portd_o_buf
.ENDMACRO

.MACRO	high_ram_write
;	cbi	PORTD,4
;	sbi	PORTD,5
;	sbi	PORTD,6
;	andi	u_portd_o_buf,0b00001111
;	ori	u_portd_o_buf,0b01101101

	ldi	u_portd_o_buf,0b01101111
	out	PORTD,u_portd_o_buf
.ENDMACRO

.MACRO	adc_latch
;	sbi	PORTD,4
;	sbi	PORTD,5
;	sbi	PORTD,6
;	ori	u_portd_o_buf,0b01111101

	ldi	u_portd_o_buf,0b01111111	
	out	PORTD,u_portd_o_buf
.ENDMACRO


.MACRO	SET_PORTB_INPUT
	clr	u_tmp			;1*
	out	DDRB,u_tmp		;1* set input
.ENDMACRO

.MACRO	SET_PORTB_OUTPUT
	ser	u_tmp
	out	DDRB,u_tmp		;1* set output
.ENDMACRO
;***** code segment 


	.cseg

	.org	$0000
	rjmp	init

	.org	INT0addr
	rjmp	ext_int0
	
	
	.org	OVF0addr
	reti

	.org	ACIaddr
	reti


;***** External int. by BCK 
ext_int0:

;
	in	x_sr,SREG	;1 store status register
dat_to_codec:
	rol	x_o_buf_l		;1 c<- outbuf_l(7)		
	rol	x_o_buf_h		;1 outbuf_h(0) <- c ,c<-outbuf_h(7)		
	andi	u_portd_o_buf,0b11111101
	brcc	out_dat_to_codec
	ori	u_portd_o_buf,0b00000010
	
out_dat_to_codec:
	out	PORTD,u_portd_o_buf
	
	in	x_portd_i_buf,PIND	;1/(2) 	|skip codec data is low
	ror	x_portd_i_buf	;1	|
	rol	x_i_buf_l		;1	|MAX 11 
	rol	x_i_buf_h		;1	|
	out	SREG,x_sr
	sbis	PIND,codec_fs	;1/2	|
	reti				;4	|
;**** max 19 cycles
;	mov	x_o_buf_l,x_i_buf_l
;	mov	x_o_buf_h,x_i_buf_h
	mov	x_o_buf_l,x_o_data_l	;1 |
	mov	x_o_buf_h,x_o_data_h	;1 |
	mov	u_i_data_l,x_i_buf_l	;1 |MAX 10
	mov	u_i_data_h,x_i_buf_h	;1 |
return:
	out	SREG,x_sr		;1 |
	reti				;4 |

;***** max 25 cycles
;first 15 bit codec data use 19 cycles 
;last bit codec data use 25 cycles 
;total 16 codec data = 19 * 15 + 25 = 310 cycles
;
	
init:	
	ldi	u_tmp,0x65
	out	0x3d,u_tmp	
	ldi	u_tmp,(1<<DDD1)+(1<<DDD4)
	OUT	DDRD,u_tmp

	ldi	u_tmp,0x40
	out	GIMSK,u_tmp		;Enable external interrupt 0
	ldi	u_tmp,0x02
	out	MCUCR,u_tmp		;on falling edges
		
	ldi	u_tmp,0b01110010	;set the portd bit direction
	out	DDRD,u_tmp

	ldi	u_tmp,0b00000100
	mov	r30,u_tmp	;u_flags
	
	SET_PORTB_INPUT
	adc_latch
	nop
	in	u_tmp,PINB
	sbrc	u_tmp,5
	rjmp	forward_mode
reverse_mode:
	ori	r30,0b00000001
	rjmp	initadc_latch
	

forward_mode:
	andi	r30,0b11111110
	ori	r30,0b00100000
	
initadc_latch:

	adc_latch	
	ldi	u_adc_pin,0b01010110	;.7 effect off 0
					;.6 bypass on  1
					;.5 x
					;.4 led  off   1
					;.3 x
					;.2 adc cs h   1
					;.1 adc clk h  1
					;.0 x
	ser	u_tmp
	out	DDRB,u_tmp
	out	PORTB,u_adc_pin
	latch_all

	clr	x_o_buf_l
	clr	x_o_buf_h
init_value:
	
	clr	u_o_ptr_l
	clr	u_o_ptr_h

	clr	x_i_buf_l
	clr	x_i_buf_h
	
	clr	u_i_data_l
	clr	u_i_data_h
	clr	x_o_data_l
	clr	x_o_data_h

	clr	x_adc_value
	clr	u_rep_val
	clr	x_adc_del
	clr	x_adc_rep

	ldi	u_tmp,0x00
	mov	x_00,u_tmp

	ldi	u_tmp,0x80
	mov	x_80,u_tmp
	
	
	ldi	u_tmp,0x7f
	mov	x_delay_h,u_tmp
	
	ldi	u_tmp,0xff
	mov	x_delay_l,u_tmp
	
	clr	u_i_ptr_l	
	clr	u_i_ptr_h

	SET_PORTB_OUTPUT
address:
	out	PORTB,u_i_ptr_l		;1*
	latch_add_l
	latch_all
				;2*
	out	PORTB,u_i_ptr_h		;1*
	latch_add_h
	latch_all

	ldi	u_tmp,0
	out	PORTB,u_tmp		;1*
	low_ram_write
	latch_all

	out	PORTB,u_tmp		;1*
	high_ram_write
	latch_all
	
	subi	u_i_ptr_l,low(-1)	;1*
	sbci	u_i_ptr_h,high(-1)	;1*
	sbrs	u_i_ptr_h,7
	brcs	address

	
	ldi	u_tmp,0b00000011	;adc_ch0
	mov	x_adc_com,u_tmp

	clr	u_adc_clk_cunt		
	clr	u_i_ptr_h

start:	sbis	PIND,3			;wait for fs high
	rjmp	start
wait_fs_low:
	sbic	PIND,3			;wait for fs low
	rjmp	wait_fs_low

	sei
	rjmp	first_begin	


wait_fs_pulse:
	latch_all
wait_fs:
	sbis	PIND,3			; wait for FS high
	rjmp 	wait_fs
fs_low:
	sbic	PIND,3			;wait for FS low
	rjmp	fs_low

		
;get the data from the memory 
first_begin:
	SET_PORTB_OUTPUT

	out	PORTB,u_o_ptr_l		;1*
	latch_add_l
	latch_all	


	out	PORTB,u_o_ptr_h		;1*
	latch_add_h
	latch_all

	SET_PORTB_INPUT

	low_ram_read			;2*
	nop
	in	x_o_data_l,PINB		;1*
	mov	u_tmp_l,x_o_data_l	;1*

	high_ram_read			;2*
	nop
	in	x_o_data_h,PINB		;1*
	mov	u_tmp_h,x_o_data_h	;1*

remain_fb_data:
	clt				;1*
	sbrs	u_tmp_h,7		;2*
	rjmp	div_8			;2
	
	set				;1*
 	com	u_tmp_l			;1*
	com	u_tmp_h			;1*
	subi	u_tmp_l,low(-1)		;1*
	sbci	u_tmp_h,high(-1)	;1*
div_8:	clc				;1*
	ror	u_tmp_h			;1*
	ror	u_tmp_l			;1*	
	clc				;1*
	ror	u_tmp_h			;1*
	ror	u_tmp_l			;1*	
	clc				;1*
	ror	u_tmp_h			;1*
	ror	u_tmp_l			;1*
	mov	u_fb_data_l,u_tmp_l
	mov	u_fb_data_h,u_tmp_h		

	

	cpi	u_rep_val,6
	breq	times_6
	cpi	u_rep_val,5
	breq	times_5
	cpi	u_rep_val,4
	breq	times_4
	cpi	u_rep_val,3
	breq	times_3
	cpi	u_rep_val,2
	breq	times_2
	cpi	u_rep_val,1
	breq	check_neq
	cpi	u_rep_val,0
	breq	times_0
	mov	u_fb_data_l,x_o_data_l
	mov	u_fb_data_h,x_o_data_h
	rjmp	save_ram	
	
times_0:clr	u_fb_data_l
	clr	u_fb_data_h
	rjmp	save_ram
		
times_2:clc
	rol	u_fb_data_l
	rol	u_fb_data_h
	rjmp	check_neq	;16

times_3:clc
	rol	u_fb_data_l
	rol	u_fb_data_h
	add	u_fb_data_l,u_tmp_l
	adc	u_fb_data_h,u_tmp_h
	rjmp	check_neq	;16 t

times_4:clc
	rol	u_fb_data_l
	rol	u_fb_data_h
	clc
	rol	u_fb_data_l
	rol	u_fb_data_h
	rjmp	check_neq	;13

times_5:clc
	rol	u_fb_data_l
	rol	u_fb_data_h
	clc
	rol	u_fb_data_l
	rol	u_fb_data_h
	add	u_fb_data_l,u_tmp_l
	adc	u_fb_data_h,u_tmp_h
	rjmp	check_neq	;14

times_6:clc
	rol	u_fb_data_l
	rol	u_fb_data_h
	clc
	rol	u_fb_data_l
	rol	u_fb_data_h
	add	u_fb_data_l,u_tmp_l
	adc	u_fb_data_h,u_tmp_h
	add	u_fb_data_l,u_tmp_l
	adc	u_fb_data_h,u_tmp_h	;12

check_neq:
	brtc	save_ram		;2
	com	u_fb_data_l		;1*
	com	u_fb_data_h		;1*
	subi	u_fb_data_l,low(-1)	;1*
	sbci	u_fb_data_h,high(-1)	;1*
save_ram:
	
	SET_PORTB_OUTPUT

					;2*
	out	PORTB,u_fb_data_l	;1*
	low_ram_write
	latch_all

	out	PORTB,u_fb_data_h	;1*
	high_ram_write
	latch_all

;	sbrc	r30,0
;	rjmp	reverse

;	subi	u_o_ptr_l,low(-1)	;1
;	sbci	u_o_ptr_h,high(-1)	;1
;	cp	x_delay_l,u_o_ptr_l	;1*
;	cpc	x_delay_h,u_o_ptr_h	;1*
;	brcc	skip_init_o_ptr		;1*
;	clr	u_o_ptr_l			;1*
;	clr	u_o_ptr_h	
;	rjmp	skip_init_o_ptr

reverse:subi	u_o_ptr_l,low(1)
	sbci	u_o_ptr_h,high(1)
	sbrs	u_o_ptr_h,7
	rjmp	skip_init_o_ptr		;1*
	mov	u_o_ptr_l,x_delay_l	;1*
	mov	u_o_ptr_h,x_delay_h	;1*

skip_init_o_ptr:

;*****89 cycles
;write data to memory 
;	sbrc	u_adc_pin,6
;	rjmp	skip_change
;	ori	u_adc_pin,0b00010000
;	cpi	u_i_ptr_h,0x08
;	brlo	skip_change
;	andi	u_adc_pin,0b11101111
skip_change:
	
	SET_PORTB_OUTPUT		;2*
	out	PORTB,u_i_ptr_l		;1*
	latch_add_l
	latch_all

				;2*
	out	PORTB,u_i_ptr_h		;1*
	latch_add_h
	latch_all

	SET_PORTB_INPUT
	
	low_ram_read
	nop
	in	u_tmp_l,PINB
	
	
	high_ram_read
	nop
	in	u_tmp_h,PINB

	sbrc	u_i_data_h,7
	rjmp	neg_i
	sbrc	u_tmp_h,7
	rjmp	pos_neg

two_pos:
	add	u_i_data_l,u_tmp_l
	adc	u_i_data_h,u_tmp_h
	brvc	non_over_flow
	ldi	u_i_data_l,0xff
	ldi	u_i_data_h,0x7f
	rjmp	non_over_flow

	
neg_i:	sbrs	u_tmp_h,7
	rjmp	pos_neg
	
two_neg:
	add	u_i_data_l,u_tmp_l
	adc	u_i_data_h,u_tmp_h 
	brpl	max_neg
	clr	u_tmp
	cp	u_i_data_l,x_00
	cpc	u_i_data_h,x_80
	brcc	non_over_flow
	
max_neg:ldi	u_i_data_l,0x01
	ldi	u_i_data_h,0x80
	rjmp	non_over_flow
	

pos_neg:
	add	u_i_data_l,u_tmp_l
	adc	u_i_data_h,u_tmp_h

non_over_flow:

	SET_PORTB_OUTPUT	 

	out	PORTB,u_i_data_l		;1*
	low_ram_write
	latch_all

	out	PORTB,u_i_data_h		;1*
	high_ram_write
	latch_all
	
	subi	u_i_ptr_l,low(-1)	;1*
	sbci	u_i_ptr_h,high(-1)	;1*
	cp	x_delay_l,u_i_ptr_l	;1*
	cpc	x_delay_h,u_i_ptr_h	;1*
	brcc	skip_init_i_ptr		;1*
	clr	u_i_ptr_l			;1*
	clr	u_i_ptr_h	
	
			;1*
skip_init_i_ptr:
	
;*****110 cycles
	
	ldi	u_tmp,0b11010111
	out	DDRB,u_tmp		;1* bit0-2 out, bit3 input

	sbrc	r30,6		;check switch flag
	rjmp	detect_sw
	sbrs	r30,2		;check 0 adc data ready	
	rjmp	process_adc_data	;2

adc_process:
		
	andi	u_adc_pin,0b11111011	;clear adc cs pin for selection
	sbrc	u_adc_pin,adc_clk		;*1/2
	rjmp	adc_clk_to_low		;2

adc_clk_to_high:
	ori	u_adc_pin,0b00000010	;set adc clock pin
	inc	u_adc_clk_cunt
	cpi	u_adc_clk_cunt,14	;
	brcc	adc_data_fully_rec
	cpi	u_adc_clk_cunt,6
	brcc	rec_adc_data
	cpi	u_adc_clk_cunt,4
	brcc	set_rec_adc_flags
	out	PORTB,u_adc_pin
	adc_latch
;	latch_all
	rjmp	wait_fs_pulse

set_rec_adc_flags:
	
	ori	r30,0b00000010	;set the receving data flag
	out	PORTB,u_adc_pin
	adc_latch
;	latch_all
	rjmp	wait_fs_pulse
		

adc_data_fully_rec:
	ori	r30,0b01000000	;set detect swtich flag	
	clr	u_adc_clk_cunt
	ori	u_adc_pin,0b00000100	;set adc cs pin
	out	PORTB,u_adc_pin
	adc_latch
;	latch_all
	rjmp	wait_fs_pulse

rec_adc_data:
	out	PORTB,u_adc_pin
	adc_latch
	clc
	sbic	PINB,3		;1
	sec			;1
	rol	x_adc_value	;1
;	latch_all
	rjmp 	wait_fs_pulse		


detect_sw:
	out	PORTB,u_adc_pin
	adc_latch
	andi	r30,0b10111011	;clear the detect sw flag,
				;clear the adc data 've processed 
	in	u_tmp,PINB
	sbrc	u_tmp,5		;switch press or not
	rjmp	switch_press
;	latch_all	
	andi	r30,0b11011111
	rjmp	wait_fs_pulse

switch_press:
	sbrc	r30,5	;check the sw pressed process already 
	rjmp	return2
	ori	r30,0b00100000	;set the switch pressed flag
	ldi	u_tmp,0b00010000	;toggle the switch register pin
	eor	r30,u_tmp
have_processed:
	sbrc	r30,4	;check enable effect or not
	rjmp	on_effect
bypass:
	andi	u_adc_pin,0b01111111	;clear the effect pin
	ori	u_adc_pin,0b01010000	;set the bypass pin 
	out	PORTB,u_adc_pin

return2:;latch_all
	rjmp	wait_fs_pulse

on_effect:
	andi	u_adc_pin,0b10101111	;clear bypass,clear the led
	ori	u_adc_pin,0b10000000	;set the effect
	out	PORTB,u_adc_pin
	latch_all
	rjmp	init_value


adc_clk_to_low:
	
	andi	u_adc_pin,0b11111101	;clear adc clk 
	sbrc	r30,1		;check the adc receive data flag
	rjmp	receiving_adc_dat
adc_command_out:
	ror	x_adc_com
	brcc	zero
one:	ori	u_adc_pin,0b00000001
	rjmp	cont
zero:	andi	u_adc_pin,0b11111110
	
cont:	out	PORTB,u_adc_pin
	adc_latch
	nop
;	latch_all
	rjmp	wait_fs_pulse	

receiving_adc_dat:
	out	PORTB,u_adc_pin
	adc_latch
	nop
;	latch_all
	rjmp	wait_fs_pulse

		

***************		
process_adc_data:
	ori	r30,0b00000100	;set the adc data have processed flag
	andi	r30,0b11111101
	sbrc	r30,delay_dat_f					
	rjmp	delay_process
repeat_process:
	ori	r30,0b00001000	;change next adc data for delay
	ldi	u_tmp,0b00000111	;adc_ch1
	mov	x_adc_com,u_tmp
	mov	u_tmp,x_adc_value
	andi	u_tmp,0b11111000
	cp	u_tmp,x_adc_rep
	breq	return4	
	mov	x_adc_rep,u_tmp

	cpi	u_tmp,223
	brcc	repeat_7
	cpi	u_tmp,191
	brcc	repeat_6
	cpi	u_tmp,159
	brcc	repeat_5
	cpi	u_tmp,127
	brcc	repeat_4
	cpi	u_tmp,95
	brcc	repeat_3
	cpi	u_tmp,65
	brcc	repeat_2	
	cpi	u_tmp,31
	brcc	repeat_1
	clr	u_rep_val
return4:
	rjmp	wait_fs_pulse
repeat_7:
	ldi	u_rep_val,7
	rjmp	wait_fs_pulse
repeat_6:
	ldi	u_rep_val,6
	rjmp	wait_fs_pulse
repeat_5:
	ldi	u_rep_val,5
	rjmp	wait_fs_pulse
repeat_4:
	ldi	u_rep_val,4
	rjmp	wait_fs_pulse
repeat_3:
	ldi	u_rep_val,3
	rjmp	wait_fs_pulse
repeat_2:
	ldi	u_rep_val,2
	rjmp	wait_fs_pulse
repeat_1:
	ldi	u_rep_val,1
	rjmp	wait_fs_pulse
	
delay_process:
	andi	r30,0b11110111
	ldi	u_tmp,0b00000011
	mov	x_adc_com,u_tmp

	ldi	u_tmp,0xff
	cp	x_adc_value,u_tmp
	breq	max_delay

	ldi	u_tmp,0b11111000
	and	x_adc_value,u_tmp	
	
	cp	x_adc_del,x_adc_value
	breq	return3

	mov	x_adc_del,x_adc_value

	clr	u_i_ptr_l
	clr	u_o_ptr_l
	clr	u_i_ptr_h
	clr	u_o_ptr_h

	ldi	u_tmp,0x15
	cp	x_adc_value,u_tmp
	brlo	min_delay
	
	clr	x_delay_h
	clc
	mov	x_delay_l,x_adc_value
		
	rol	x_delay_l
	rol	x_delay_h
	
	rol	x_delay_l
	rol	x_delay_h
	
	rol	x_delay_l
	rol	x_delay_h
	
	rol	x_delay_l
	rol	x_delay_h
	
	rol	x_delay_l
	rol	x_delay_h

	rol	x_delay_l
	rol	x_delay_h

	rol	x_delay_l
	rol	x_delay_h

		

return3:
	rjmp	wait_fs_pulse


max_delay:
	ldi	u_tmp,0xff
	mov	x_delay_l,u_tmp
	ldi	u_tmp,0x7f
	mov	x_delay_h,u_tmp
	rjmp	wait_fs_pulse

min_delay:	
	ldi	u_tmp,0xff
	mov	x_delay_l,u_tmp
	clr	x_delay_h
	rjmp	wait_fs_pulse