dr-1.asm

单片机音频信号处理软件1.

.include  "1200def.inc"

;***** Global Registers

.def	x_sr		=r0	;
.def	x_o_buf_l	=r1	;codec output buffer register
.def	x_o_buf_h	=r2
.def	x_i_buf_l	=r3	;codec input buffer register
.def	x_i_buf_h	=r4
.def	x_adc_com	=r5
.def	x_adc_value	=r6
.def	x_o_data_l	=r7	;codec output data register
.def	x_o_data_h	=r8
.def	x_delay_h	=r9
.def	x_portd_i_buf	=r10
.def	x_flags		=r11
.def	x_rep_val	=r12
.def	x_adc_clk_cunt	=r13

.def	u_tmp		=r16
.def	u_tmp_l		=r17
.def	u_tmp_h		=r18
.def	u_adc_pin	=r19
.def	u_i_data_l	=r20	;codec input data register
.def	u_i_data_h	=r21	
.def	old_value_l	=r22
.def	old_value_h	=r23
.def	u_fb_data_l	=r24
.def	u_fb_data_h	=r25
.def	u_o_ptr_l	=r26
.def	u_o_ptr_h	=r27
.def	u_i_ptr_l	=r28
.def	u_i_ptr_h	=r29
.def	u_flags		=r30
.def	u_portd_o_buf	=r31



;***** Constant


.equ	codec_do	= 0

.equ	codec_bck	= 2
.equ	codec_fs	= 3
.equ	adc_ch0		= 3
.equ	adc_ch1		= 7
.equ	adc_dat_rdy_f	= 2
.equ	k_adc_dat_rdy_f	= 0b00000100
.equ	adc_rec_act_f	= 1
.equ	k_adc_rec_act_f	= 0b00000010	
.equ	adc_di		= 0
.equ	k_adc_di	= 0b00000001
.equ	adc_clk		= 1
.equ	k_adc_clk_pin	= 0b00000010
.equ	k_adc_cs_pin	= 0b00000100
.equ	adc_cs		= 2
.equ	adc_do		= 0
.equ	last_adc_data_clk 	= 13
.equ	last_adc_com_clk	= 5
.equ	by_pass_mode = 0b01010110
.equ	delay_dat_f	= 3
.equ	k_delay_dat_f	= 0b00001000
.equ	enable_effect_f	= 4
.equ	k_toggle_sw	= 0b00010000
.equ	led_pin		= 4
.equ	k_led_pin	= 0b00010000

.equ	adc_sw_dir		= 0b11010111
.equ	sw_pin		= 5
.equ	sw_pressed_f	= 5
.equ	k_sw_pressed_f	= 0b00100000
.equ	effect_latch	= 7
.equ	k_effect_latch	= 0b10000000
.equ	bypass_latch	= 6
.equ	k_bypass_latch	= 0b01000000

	

;flags define
;	match level 	0
;	x		1
;	adc process	2
;	adc repeat	3
;	adc delay 	4
;	adc mix		5
;	adc onoff	6
;	x		7	

;x_flags
;	pressed		0
;	toggle		1
;	effect		2

.MACRO	latch_all
	ldi	u_portd_o_buf,0b00001111
	out	PORTD,u_portd_o_buf
	
.ENDMACRO

.MACRO	latch_add_l
	ldi	u_portd_o_buf,0b00011111
	out	PORTD,u_portd_o_buf
	nop
.ENDMACRO

.MACRO	latch_add_h
	ldi	u_portd_o_buf,0b00101111
	out	PORTD,u_portd_o_buf
	nop
.ENDMACRO

.MACRO	low_ram_read
	ldi	u_portd_o_buf,0b00111111
	out	PORTD,u_portd_o_buf
	
.ENDMACRO

.MACRO	high_ram_read
	ldi	u_portd_o_buf,0b01001111
	out	PORTD,u_portd_o_buf

	
.ENDMACRO

.MACRO	low_ram_write
	ldi	u_portd_o_buf,0b01011111
	out	PORTD,u_portd_o_buf
	
	
.ENDMACRO

.MACRO	high_ram_write
	ldi	u_portd_o_buf,0b01101111
	out	PORTD,u_portd_o_buf
.ENDMACRO

.MACRO	adc_latch
	ldi	u_portd_o_buf,0b01111111	
	out	PORTD,u_portd_o_buf
.ENDMACRO


.MACRO	SET_PORTB_INPUT
	clr	u_tmp			;1*
	out	DDRB,u_tmp		;1* set input
.ENDMACRO

.MACRO	SET_PORTB_OUTPUT
	ser	u_tmp
	out	DDRB,u_tmp		;1* set output
.ENDMACRO
;*************************** code segment 
	.cseg
	.org	$0000
	rjmp	init

	.org	INT0addr
	rjmp	ext_int0
	
	.org	OVF0addr
	reti

	.org	ACIaddr
	reti

;************************** External int. by BCK 
ext_int0:

	in	x_sr,SREG	;1 store status register
dat_to_codec:
	rol	x_o_buf_l		;1 c<- outbuf_l(7)		
	rol	x_o_buf_h		;1 outbuf_h(0) <- c ,c<-outbuf_h(7)		
	andi	u_portd_o_buf,0b11111101
	brcc	out_dat_to_codec
	ori	u_portd_o_buf,0b00000010
out_dat_to_codec:
	out	PORTD,u_portd_o_buf
	in	x_portd_i_buf,PIND	;skip codec data is low
	ror	x_portd_i_buf			
	rol	x_i_buf_l		 
	rol	x_i_buf_h	
	out	SREG,x_sr
	reti	
	
;*********************************************************		
init:	
;	ldi	u_tmp,0x65
;	out	0x3d,u_tmp	
	ldi	u_tmp,(1<<DDD1)+(1<<DDD4)
	out	DDRD,u_tmp

	ldi	u_tmp,0x40
	out	GIMSK,u_tmp		;Enable external interrupt 0
	ldi	u_tmp,0x02
	out	MCUCR,u_tmp		;on falling edges
		
	ldi	u_tmp,0b01110010	;set the portd bit direction
	out	DDRD,u_tmp

	
	
	ldi	u_tmp,0x7f
	mov	x_delay_h,u_tmp
	
	


initadc_latch:

	adc_latch	
	ldi	u_adc_pin,0b00001111	;.7 x
					;.6 x
					;.5 x
					;.4 x
					;.3 led off    1
					;.2 adc cs h   1
					;.1 adc clk h  1
					;.0 adc di     1
	ser	u_tmp
	out	DDRB,u_tmp
	out	PORTB,u_adc_pin
	latch_all

	clr	x_adc_value
	clr	x_rep_val
	clr	x_flags

;********************************
clr_ext_mem:	
	ldi	u_tmp_h,0x7f
	clr	u_tmp_l
	clr	u_tmp
	
	SET_PORTB_OUTPUT			

addressing:
	out	PORTB,u_tmp_l		
	latch_add_l
	latch_all

	out	PORTB,u_tmp_h		
	latch_add_h
	latch_all

	out	PORTB,u_tmp	
	low_ram_write
	latch_all

	out	PORTB,u_tmp		
	high_ram_write
	latch_all

	subi	u_tmp_l,low(1)
	sbci	u_tmp_h,high(1)
	brpl	addressing	
;*********************************
;init value	
	clr	x_i_buf_l
	clr	x_i_buf_h
	
	clr	x_o_data_l
	clr	x_o_data_h

	clr	u_tmp_l
	clr	u_tmp_h

	ldi	u_tmp,0b00000011	;adc_ch0
	mov	x_adc_com,u_tmp

	clr	x_adc_clk_cunt		
	ldi	u_tmp,0b00001100	;adc process flag, adc repeat
	mov	r30,u_tmp		;u_flags

	clr	u_o_ptr_l	
	clr	u_o_ptr_h	
	clr	u_i_ptr_l
	clr	u_i_ptr_h
;*********************************
start:	sbis	PIND,3			;wait for fs high
	rjmp	start

	mov	x_o_buf_l,x_o_data_l	
	mov	x_o_buf_h,x_o_data_h	
	mov	u_i_data_l,x_i_buf_l	
	mov	u_i_data_h,x_i_buf_h	
	sei
	rjmp	prepare_data_from_ram	

wait_fs_pulse:
	latch_all
wait_fs:
	sbis	PIND,3			; wait for FS high
	rjmp 	wait_fs	 	;*** notice: don't check bck
	mov	x_o_buf_l,x_o_data_l	
	mov	x_o_buf_h,x_o_data_h	
	mov	u_i_data_l,x_i_buf_l	
	mov	u_i_data_h,x_i_buf_h	
		
;***************************************** 
prepare_data_from_ram:
	SET_PORTB_OUTPUT

	out	PORTB,u_o_ptr_l		
	latch_add_l
	latch_all	

	out	PORTB,u_o_ptr_h		
	latch_add_h
	latch_all

	SET_PORTB_INPUT
	
	low_ram_read	
	nop	
	in	x_o_data_l,PINB		
	
	high_ram_read	
	nop	
	in	x_o_data_h,PINB		
	
	sbrs	u_flags,0		;crossing flag
	rjmp	remain_fb_data
	
	cp	x_o_data_h,old_value_h	;match together
	
	breq	match_data

	sbrs	old_value_h,7		;test negative value
	rjmp	positive_old_value
	
	subi	old_value_l,low(-16)	;if -ve, increment
	sbci	old_value_h,high(-16)
	brpl	keep_zero
	mov	x_o_data_h,old_value_h	;change the value
	mov	x_o_data_l,old_value_l
	rjmp	remain_fb_data

positive_old_value:
	subi	old_value_l,low(16)	; if +ve decrement
	sbci	old_value_h,high(16)
	brcs	keep_zero
	mov	x_o_data_h,old_value_h
	mov	x_o_data_l,old_value_l
	rjmp	remain_fb_data


keep_zero:
	clr	old_value_l
	clr	old_value_h
	rjmp	remain_fb_data

match_data:
	andi	u_flags,0b11111110	;if match, clear crossing flag
	
******************************************
;prepare_feedback_data_to_ram
remain_fb_data:
	

	mov	u_tmp_l,x_o_data_l	
	mov	u_tmp_h,x_o_data_h	
	clt				
	sbrs	u_tmp_h,7		
	rjmp	div_8			
	
;change to positive number
	set				
 	com	u_tmp_l			
	com	u_tmp_h			
	subi	u_tmp_l,low(-1)		
	sbci	u_tmp_h,high(-1)	
	
div_8:	mov	u_fb_data_l,u_tmp_l
	mov	u_fb_data_h,u_tmp_h

	clc				
	ror	u_tmp_h			
	ror	u_tmp_l				
	clc				
	ror	u_tmp_h			
	ror	u_tmp_l				
	clc				
	ror	u_tmp_h			
	ror	u_tmp_l			
		
	mov	u_tmp,x_rep_val
	cpi	u_tmp,6
	brge	check_neq
	cpi	u_tmp,5
	breq	times_7_8
	cpi	u_tmp,4
	breq	times_6_8
	cpi	u_tmp,3
	breq	times_4_8
	cpi	u_tmp,2
	breq	times_2_8
	cpi	u_tmp,1
	breq	times_1_8	;1_8
	
	
times_0:clr	u_fb_data_l
	clr	u_fb_data_h
	rjmp	store_fb_data

times_1_8:
	mov	u_fb_data_l,u_tmp_l
	mov	u_fb_data_h,u_tmp_h
	rjmp	check_neq
		
times_2_8:
	clc
	rol	u_tmp_l
	rol	u_tmp_h
	mov	u_fb_data_l,u_tmp_l
	mov	u_fb_data_h,u_tmp_h
	rjmp	check_neq	

times_4_8:
	clc
	ror	u_fb_data_h
	ror	u_fb_data_l
	rjmp	check_neq	

times_6_8:
	sub	u_fb_data_l,u_tmp_l
	sbc	u_fb_data_h,u_tmp_h
	sub	u_fb_data_l,u_tmp_l
	sbc	u_fb_data_h,u_tmp_h
	rjmp	check_neq	

times_7_8:
	sub	u_fb_data_l,u_tmp_l
	sbc	u_fb_data_h,u_tmp_h
	rjmp	check_neq	;14


check_neq:
	brtc	store_fb_data
	com	u_fb_data_l		
	com	u_fb_data_h		
	subi	u_fb_data_l,low(-1)	
	sbci	u_fb_data_h,high(-1)	

store_fb_data:
	SET_PORTB_OUTPUT
	
	out	PORTB,u_fb_data_l	
	low_ram_write
	latch_all

	out	PORTB,u_fb_data_h	
	high_ram_write
	latch_all

;**************************************
;prepare_data_to_ram:

	SET_PORTB_OUTPUT			
	out	PORTB,u_i_ptr_l		
	latch_add_l
	latch_all

	out	PORTB,u_i_ptr_h		
	latch_add_h
	latch_all

	SET_PORTB_INPUT
	
	low_ram_read
	nop
	in	u_tmp_l,PINB
	
	high_ram_read
	nop
	in	u_tmp_h,PINB
;******************************
	sbrc	u_i_data_h,7
	rjmp	neg_i

	sbrc	u_tmp_h,7
	rjmp	pos_neg

two_pos:
	add	u_tmp_l,u_i_data_l
	adc	u_tmp_h,u_i_data_h
	brvc	store_data_to_ram
	ser	u_tmp_l
	ldi	u_tmp_h,0x7f
	rjmp	store_data_to_ram

neg_i:	sbrs	u_tmp_h,7
	rjmp	pos_neg

two_neg:add	u_tmp_l,u_i_data_l
	adc	u_tmp_h,u_i_data_h
	subi	u_tmp_l,low(1)
	sbci	u_tmp_h,high(1)
	sbrs	u_tmp_h,7
	rjmp	max_neg
	subi	u_tmp_l,low(-1)
	sbci	u_tmp_h,high(-1)
	rjmp	store_data_to_ram

max_neg:ldi	u_tmp_l,0x01
	ldi	u_tmp_h,0x80
	rjmp	store_data_to_ram


pos_neg:
	add	u_tmp_l,u_i_data_l
	adc	u_tmp_h,u_i_data_h

;************************
store_data_to_ram:
	

store_memory:

	SET_PORTB_OUTPUT	 

	out	PORTB,u_tmp_l	
	low_ram_write
	latch_all

	out	PORTB,u_tmp_h		
	high_ram_write
	latch_all

;**************************************
;update in pointer

reverse_mode:
	cp	u_o_ptr_l,u_i_ptr_l
	cpc	u_o_ptr_h,u_i_ptr_h
	brne	skip_flaging
	ori	u_flags,0b00000001
	mov	old_value_h,x_o_data_h
	mov	old_value_l,x_o_data_l
	
skip_flaging:	
	subi	u_i_ptr_l,low(-1)
	sbci	u_i_ptr_h,high(-1)
	tst	u_i_ptr_l
	brne	update_out_ptr
	cp	x_delay_h,u_i_ptr_h
	breq	init_pointer

update_out_ptr:	
	subi	u_o_ptr_l,low(1)
	sbci	u_o_ptr_h,high(1)
	sbrs	u_o_ptr_h,7
	rjmp	beginning_at_ram_process
	mov	u_o_ptr_h,x_delay_h
	dec	u_o_ptr_h
	rjmp	beginning_at_ram_process

init_pointer:
	clr	u_o_ptr_l	
	clr	u_o_ptr_h	
	clr	u_i_ptr_l
	clr	u_i_ptr_h
	

;**************************************
beginning_at_ram_process:
	sbrc	u_flags,0	;crossing process
	rjmp	wait_fs
	

adc_processing:	
	sbrc	r30,2			;adc data receiving finished
	rjmp	adc_process

	sbrc	r30,3			;adc repeat process
	rjmp	adc_repeat

	sbrc	r30,4
	rjmp	adc_delay

	sbrc	r30,5
	rjmp	adc_mix	

on_off:
	andi	r30,0b10111111	;reset the adc data recived
	ori	r30,0b00001100	;change next adc data for repeat
	ldi	u_tmp,0b00000011	;adc ch0
	mov	x_adc_com,u_tmp
	
	sbrs	x_adc_value,7
	rjmp	no_press
	sbrc	x_flags,0		;pressed flag				
	rjmp	wait_fs
	ldi	u_tmp,0b00000001
	or	x_flags,u_tmp		;set pressed flag
	ldi	u_tmp,0b00000010
	eor	x_flags,u_tmp		;toggle flag
	sbrs	x_flags,1
	rjmp	bypass_state
	cli
	andi	u_adc_pin,0b11110111	;turn on led
	rjmp	clr_ext_mem
bypass_state:
	ori	u_adc_pin,0b00001000	;turn off led
	rjmp	off_mode

no_press:
	ldi	u_tmp,0b11111110
	and	x_flags,u_tmp
	rjmp	wait_fs	

;**************************
adc_process:
	andi	u_adc_pin,0b11111011	;clear adc cs pin for selection
	sbrc	u_adc_pin,adc_clk		
	rjmp	adc_clk_to_low		;
;**************************
adc_clk_to_high:
	ori	u_adc_pin,0b00000010	;set adc clock pin
	inc	x_adc_clk_cunt
	mov	u_tmp,x_adc_clk_cunt
	cpi	u_tmp,14	;
	brcc	adc_data_fully_rec
	cpi	u_tmp,6
	brcc	rec_adc_data
	out	PORTB,u_adc_pin
	adc_latch
	rjmp	wait_fs_pulse
	

adc_data_fully_rec:
	andi	r30,0b11111011		;	
	clr	x_adc_clk_cunt
	ori	u_adc_pin,0b00000100	;set adc cs pin
	out	PORTB,u_adc_pin
	adc_latch
	rjmp	wait_fs_pulse

rec_adc_data:
	ldi	u_tmp,0b11111110
	out	DDRB,u_tmp	

	out	PORTB,u_adc_pin		;*** notice the adco normal
	adc_latch
	nop		;time delay ,do not mov
	sec
	sbic	PINB,0		
	clc			
	rol	x_adc_value	
	rjmp 	wait_fs_pulse	

;***********************************
adc_clk_to_low:
	
	andi	u_adc_pin,0b11111101	;clear adc clk 
	ror	x_adc_com
	brcc	zero

one:	ori	u_adc_pin,0b00000001
	rjmp	cont
zero:	andi	u_adc_pin,0b11111110
	
	
cont:	out	PORTB,u_adc_pin
latch_adc:
	adc_latch
	rjmp	wait_fs_pulse	

;***************************************		
adc_repeat:
	andi	r30,0b11110111	;reset the adc data received 
	ori	r30,0b00010100	;change next adc data for delay
	ldi	u_tmp,0b00000111	;adc_ch1
	mov	x_adc_com,u_tmp
	
	mov	x_rep_val,x_adc_value
	lsr	x_rep_val
	lsr	x_rep_val
	lsr	x_rep_val
	lsr	x_rep_val
	lsr	x_rep_val
	rjmp	wait_fs
;***************************************	
adc_delay:
	andi	r30,0b11101111	;reset the adc data received
	ori	r30,0b00100100	;change next adc data for mix
	ldi	u_tmp,0b00001011	;adc ch2
	mov	x_adc_com,u_tmp
	ldi	u_tmp,0b00001100
	add	x_adc_value,u_tmp
	brcc	not_max
	ser	u_tmp
	mov	x_adc_value,u_tmp
not_max:	
	clc
	ror	x_adc_value
	mov	x_delay_h,x_adc_value
	rjmp	wait_fs

;**************************************
adc_mix:
	andi	r30,0b11011111	;reset the adc data received 
	ori	r30,0b01000100	;change next adc data for on off
	ldi	u_tmp,0b00001111	;adc_ch3
	mov	x_adc_com,u_tmp

	sbrc	u_adc_pin,3
	rjmp	off_mode

	mov	u_tmp,x_adc_value
	cpi	u_tmp,3
	brlo	p3
	cpi	u_tmp,58
	brlo	p3_e1
	cpi	u_tmp,106
	brlo	p3_e2
	cpi	u_tmp,159
	brlo	p3_e3
	cpi	u_tmp,198
	brlo	p2_e3
	cpi	u_tmp,253
	brlo	p1_e3
e3:	ldi	u_adc_pin,0b11000111	
	rjmp	wait_fs
p3:	ldi	u_adc_pin,0b00110111	
	rjmp	wait_fs
p3_e1:	ldi	u_adc_pin,0b01110111	
	rjmp	wait_fs
p3_e2:	ldi	u_adc_pin,0b10110111	
	rjmp	wait_fs
p3_e3:	ldi	u_adc_pin,0b11110111	
	rjmp	wait_fs
p2_e3:	ldi	u_adc_pin,0b11010111	
	rjmp	wait_fs
p1_e3:	ldi	u_adc_pin,0b11100111
	rjmp	wait_fs

off_mode:
	ldi	u_adc_pin,0b00111111
	rjmp	wait_fs

;**********************************