testutil.cpp

一个amccs5933芯片的驱动程序开发源程序和部分文档

		unsigned long Length;

    //////////////////////////////////////////////////////////////////////
    // Contact the driver
    //////////////////////////////////////////////////////////////////////
	//returnCode = comemOpenDriverL(comemID);	//FXN
	if(comemID < 8)	//FXN
		returnCode = OpenPCIDP(comemID, &PCIDPHandle[comemID]);	//FXN
	else
		returnCode = 87;	//FXN ERROR_INVALID_PARAMETER

    if (returnCode != NO_ERROR)
        {
        reportErrorCodeL(returnCode, "opening driver: PCIDP card may not be present in your PC");
        return(1);
        }

	if (chipType() == CHIP3041)	//FXN
		Length = 512;				// For 3041, in bytes.	//FXN

	else	//FXN
		Length = 0x8000;		// For 3042, in bytes.	//FXN

	returnCode = MapBaseRegister(	//FXN
		PCIDPHandle[comemID],	//FXN
		0,	//FXN
		&Length,	//FXN
		&PCIDPMemory[comemID],	//FXN
		&IOMemory,	//FXN
		&IOSpace	//FXN
	);	//FXN

	if (returnCode != NO_ERROR){	//FXN
		reportErrorCodeL(returnCode, "mapping to board memory");	//FXN
		return(1);	//FXN
	}	//FXN

	return(0);
}

DWORD doDMA(DWORD hostPhys,		// host-side physical address
			DWORD SMstart,		// shared mem start address
			DWORD DMAlength,	// DMA Length
			DWORD DMAdir,		// DMA Direction
			DWORD comemID)
{
	DWORD errorCnt = 0;
    
    DWORD linBAR[COMEM_MAX_BARS];
		linBAR[0] = (DWORD)PCIDPMemory[comemID];	//FXN
    //DWORD returnCode = comemCopyBarPtrL(linBAR, comemID);	//FXN
		DWORD returnCode = NO_ERROR;	//FXN
    if (returnCode != NO_ERROR)
    {
		reportErrorCode(returnCode, "creating BAR pointers.");
		errorCnt++;
    }

	// check arbitration bits. // TPM: MUST make volatile for release version
	volatile struct op_regs_struct_42_t * regp = (struct op_regs_struct_42_t *) (linBAR[0] + OP_REGS_BASE_42);
	char tempc;

	// The L and P bits should both be zero (neither side claims the DMA resource)
	//printf("Checking L and P bits: &(regp->dmactl_v.dmactl_bytes[1])=%08x\n", &(regp->dmactl_v.dmactl_bytes[1]));
	if ((tempc = regp->dmactl_v.dmactl_bytes[1]) != 0)
	{
		errorCnt++;
		printf ("  dmactl LP bits - bad initial state. Read %02x. Should be 00. Errs=%d\n", 
				tempc,                   errorCnt);
	}

	// Write all ones to the LP byte.  Only the P bit should set.		
	regp->dmactl_v.dmactl_bytes[1] = 0xFF;

	if ((tempc = regp->dmactl_v.dmactl_bytes[1]) != 1)
	{
		errorCnt++;
		printf ("  dmactl LP bits - P bit should be set. Read %02x. Should be 01. Errs=%d\n",
				    tempc,                   errorCnt);
	}

	// Write all zeros to the LP byte.  We should be able to reset the P bit.		
	regp->dmactl_v.dmactl_bytes[1] = 0;

	if ((tempc = regp->dmactl_v.dmactl_bytes[1]) != 0)
	{
		errorCnt++;
		printf ("  dmactl LP bits - P bit should be reset. Read %02x. Should be 00. Errs=%d\n",
					tempc,                   errorCnt);
	}

	regp->dmalbase = SMstart;
	regp->dmasize = DMAlength - 4; // must be reduced by one DWORD
	regp->dmahbase = hostPhys;

	// Check to make sure that the DMA complete bit is not already set 
	//  (not normally required, but part of a resonable test).
	if (regp->hint & DMA_COMPLETE_BIT)
	{	errorCnt++;
		printf ("Error: DMA_COMPLETE_BIT should not be set. Errs=%d\n", errorCnt);
	}

	// Show the time in mSec for the DMA
	LARGE_INTEGER llnHPTimerFreq;	// High Performance Timer: Frequency
	LARGE_INTEGER llnHPT1;			// High Performance Timer: Time 1
	LARGE_INTEGER llnHPT2;			// High Performance Timer: Time 2
	LARGE_INTEGER llnT_uSec;		// Time in microseconds
	QueryPerformanceFrequency(&llnHPTimerFreq);
	QueryPerformanceCounter(&llnHPT1);

	// Write low-order byte of DMACTL to KICK OFF the DMA. 
	regp->dmactl_v.dmactl_bytes[0] = (volatile unsigned char)DMAdir;

	// Wait for the DMA complete bit to be set.
	DWORD timeout = DMAlength * DMAlength;  // Give mucho time to complete.
	while ( ((regp->hint & DMA_COMPLETE_BIT) != DMA_COMPLETE_BIT) && timeout )
		timeout--;							// busy loop while doing DMA

	if (timeout == 0)
	{
		errorCnt++;
		printf ("Error: timed out before DMA_COMPLETE_BIT set (DMA completed). Errs=%d\n", errorCnt);
	}
	else
	{
		if(QueryPerformanceCounter(&llnHPT2))
		{
			llnT_uSec.QuadPart = ( (llnHPT2.QuadPart - llnHPT1.QuadPart) * // Time Delta
				                    ((LONGLONG)1E9/llnHPTimerFreq.QuadPart) ) / 
								   (LONGLONG)1E3; // could divide by 1E9 for Time in Sec
			//printf("DMA_COMPLETE_BIT set (DMA completed) in %3d Sec: %03d mSec: %03d  uSec\n", 
			//	llnT_uSec.LowPart/(LONG)1E6, (llnT_uSec.LowPart/(LONG)1E3)%(1000), (llnT_uSec.LowPart)%(1000));
//			printf("DMA completed in %3d Sec: %03d mSec: %03d  uSec: DMA Rate = %d Mb/Sec\n", 
//				llnT_uSec.LowPart/(LONG)1E6, (llnT_uSec.LowPart/(LONG)1E3)%(1000), 
//				(llnT_uSec.LowPart)%(1000), (1000000/llnT_uSec.LowPart)/(1048576/DMAlength));
		}
	}

	return (errorCnt);

}  // end doDMA()

DWORD testDMAtoTarg(DWORD comemID)
{
	DWORD errorCnt = 0;
	DWORD linPage;
	DWORD physPage;
	
	printf ("Testing DMA to Target...\n");

	// Use comemAllocContigMemL to get a 32K contiguous buffer in host memory.
    //DWORD returnCode = comemAllocContigMemL(4, &linPage, &physPage, comemID);	//FXN
		DWORD returnCode = MapDMAMemory(PCIDPHandle[comemID], (unsigned long**)&linPage, &physPage);	//FXN
    if (returnCode != NO_ERROR)
	{
		printf("Error Allocating Contiguous Memory\n");
        return(++errorCnt);
	}
	
	DWORD* hostPhys  = (DWORD*)physPage;
	DWORD* hostLin = (DWORD*)linPage;
	DWORD SMstart = 0;
	//DWORD DMAsize  = 0x1000;
	DWORD DMAsize  = 0x4000;
	
	// Initialize source buffer
	printf ("Initializing source at: 0x%08x DMAsize: 0x%x pattern=ADDR_PATTERN\n", hostLin, DMAsize);
	for (DWORD i = 0 ; i < DMAsize/4 ; i++)
		hostLin[i] = i;					// initialize the DMA source area

	// Write a pattern to destination (Shared Mem)  so the HOST has to actually change it.
	initSharedMem (SMstart, DMAsize, FILL_PATTERN, comemID);

	// Perform DMA operation using doDMA
	errorCnt += doDMA ( (DWORD)hostPhys,// hostphys (host-side physical address)
						SMstart,		// shared mem start (first byte of shared mem = address 0)
						DMAsize,		// size of DMA
						0,				// directionTo3042 = 0
						comemID);

	// Check the destination buffer
	errorCnt = checkSharedMem (SMstart, DMAsize, ADDR_PATTERN, comemID);

	// Deallocate buffer in host memory.
	//comemDeAllocContigMemL(&linPage, &physPage, comemID);	//FXN
	UnMapDMAMemory(PCIDPHandle[comemID], (unsigned long*)linPage);	//FXN

	return(errorCnt);
}

// testDMAtoHost
// Test DMA functionality by performing a DMA operation from the 3042 to the Host.
// Use comemAllocContigMemL to get a 32K contiguous buffer in host memory.
// Initialize source buffer (Shared Mem).
// Write a pattern to destination buffer so the HOST has to actually change it.
// Perform DMA operation using doDMA
// Check the destination buffer.
// Deallocate buffer in host memory.
//
DWORD testDMAtoHost(DWORD comemID)
{
	DWORD linPage;
	DWORD physPage;
	int errorCnt = 0;
	DWORD i;

	printf ("Testing DMA to Host...\n");

	// Use comemAllocContigMemL to get a 32K contiguous buffer in host memory.
    //DWORD returnCode = comemAllocContigMemL(4, &linPage, &physPage, comemID);	//FXN
		DWORD returnCode = MapDMAMemory(PCIDPHandle[comemID], (unsigned long**)&linPage, &physPage);	//FXN
    if (returnCode != NO_ERROR)
    {
        printf("Error creating BAR pointers.");
		return (returnCode);
    }

	DWORD* hostPhys  = (DWORD*)physPage;
	DWORD* hostLin = (DWORD*)linPage;
	DWORD SMstart = 0;
	//DWORD DMAsize  = 0x1000;
	DWORD DMAsize  = 0x4000;

	// Initialize source buffer (Shared Mem)
	initSharedMem(SMstart, DMAsize, ADDR_PATTERN, comemID);
				
	// Write a pattern to destination buffer so the HOST has to actually change it.
	printf ("Initializing destination buffer at: 0x%08x pattern=0xFEEDBEEF\n", hostLin);
	for (i = 0 ; i < DMAsize/4 ; i++)
		hostLin[i] = 0xFEEDBEEF;		// initialize the DMA destination area

    // Perform DMA operation using doDMA
	errorCnt += doDMA ( (DWORD)hostPhys,// hostphys (host-side physical address)
						SMstart,		// shared mem start (first byte of shared mem = address 0)
						DMAsize,		// size of DMA
						1,				// directionToHost = 1
						comemID);

	// Check the destination buffer
	for (i = 0 ; i < DMAsize/4 ; i++)
	{
		if (hostLin[i] != i)
		{
			if(errorCnt++ < 8) // only report first 8 errors
			{
				printf ("Error: PCIAddr=%08x LocalAddr=%08x Wrote=%08x Read=%08x\n", 
					hostLin+i, i, i, hostLin[i]);
			}
		}
	}

	// Deallocate buffer in host memory.
	//comemDeAllocContigMemL(&linPage, &physPage, comemID);	//FXN
	UnMapDMAMemory(PCIDPHandle[comemID], (unsigned long*)linPage);	//FXN

	return(errorCnt);
}

// Set up the operation register masks.  The masks are need on the bits that comem lite can
// change internally. A one designates a masked bit.                          1098 7654 3210 9876 5432 1098 7654 3210
//    op_register_mask_memory [ `I2C_COMMAND_REG >> 2 ]                       = 32'b1111_1111_1111_1111_1111_1111_1111_1111;
//    op_register_mask_memory [ `I2C_READ_DATA_REG >> 2 ]                     = 32'b1111_1111_1111_1111_1111_1111_1111_1111;
//    op_register_mask_memory [ `I2C_STATUS_REG >> 2 ]                        = 32'b0000_0000_0000_0000_0000_0000_1110_0001;
//    op_register_mask_memory [ `DMA_CONTROL_REG >> 2 ]                       = 32'b0000_0000_0000_0000_0000_0011_0000_0000;
//    op_register_mask_memory [ `HOST_INTERRUPT_CONTROL_STATUS_REG >> 2 ]     = 32'b0000_0000_1100_0000_0000_0011_1111_1011;
//    op_register_mask_memory [ `LOCAL_INTERRUPT_CONTROL_STATUS_REG >> 2 ]    = 32'b0000_0000_1100_0000_0000_0011_1110_1011;
//
// testOpRegsBits: Basically, do walking 1's test (rotate 1 through all bits).
// After writing bits that are writable, check to make sure everything else is OK.
//
//
DWORD testOpRegsBits(DWORD comemID)
{
	printf ("Testing Op Regs Bits...\n");
	return(0);
}

//  testReset: Reset target and check values to confirm proper reset.
DWORD testReset(DWORD comemID)
{
	DWORD dwBarBase;
//	DWORD volatile * dwpBarBase;
	DWORD linBAR[COMEM_MAX_BARS];
		linBAR[0] = (DWORD)PCIDPMemory[comemID];	//FXN
    //DWORD returnCode = comemCopyBarPtrL(linBAR, comemID);	//FXN
		DWORD returnCode = NO_ERROR;	//FXN
	if (returnCode != NO_ERROR)
	{
		printf("Error creating BAR pointers.");
		return(1);
	}
	dwBarBase = linBAR[0]; // Get a pointer to the Shared Memory area (BAR 0)
//	dwpBarBase = (DWORD volatile *) linBAR[0]; // Get a pointer to the Shared Memory area (BAR 0)
//	dwpBarBase = linBAR[0]; // Get a pointer to the Shared Memory area (BAR 0)

//  0. Set Local Bus Reset State
//    a. For PCI tests, hold Local processor in reset: write 0x00000001 to 0x04E0
//  1. Reset FIFO flags
//    a. PCI can do a Soft Reset
	*(DWORD volatile *)(dwBarBase+ADDR_HCTL) = 0x00000003; // Soft Reset
	*(DWORD volatile *)(dwBarBase+ADDR_HCTL) = 0x00000001; // Local processor in reset
//	dwpBarBase[ADDR_HCTL] = 0x00000003;
//	dwpBarBase[ADDR_HCTL] = 0x00000001;
//  2. Set I2O Mask Registers for both I2OHIMR AND I2OLISR
//    a. write 0xFFFFFFFF to 0x0034
//    b. write 0xFFFFFFFF to 0x003C
//	*(DWORD*)(dwBarBase+0x0034) = 0xFFFFFFFF;  __BBX Soft Reset initializes mask
//	*(DWORD*)(dwBarBase+0x003C) = 0xFFFFFFFF;  __BBX Soft Reset initializes mask
//  2.5 Check DMA Control Arbitration bits, (PI and W not cleared by Soft Reset)
//  3. Clear Interrupt Registers for both HINT and LINT
//    a. write 0x0000FFFF to 0x04E4
//    b. write 0x0000FFFF to 0x04F4
//	dwpBarBase[ADDR_HINT] = 0x0000FFFF;
//	dwpBarBase[ADDR_LINT] = 0x0000FFFF;
	*(DWORD volatile *)(dwBarBase+ADDR_HINT) = 0x0000FFFF;
	*(DWORD volatile *)(dwBarBase+ADDR_LINT) = 0x0000FFFF;
//  4. Confirm reset and constant conditions
//    a. Execute an approximate 1 second pause after the prior writes
//    b. Read and Confirm the following DWORD values:
//         DMACTL   0x04BC  0x0000000X  __BBX Add check for DMA Arb bits[9,8]
//         ARBUTIL  0x04C0  0x00000000  __BBX Update for Rev B
//         HCTL     0x04E0  0x00000001  (for PCI side testing)
//         HINT     0x04E4  0x00000000
//         LINT     0x04F4  0x00000000
//         LBUSCFG  0x04FC  0x00010B50  __BBX Only reset with RST#, not soft reset
//         I2OHISR  0x0030  0x00000000
//         I2OHIMR  0x0034  0xFFFFFFFF
//         I2OLISR  0x0038  0x00000000
//         I2OLIMR  0x003C  0xFFFFFFFF
//         I2OIBF   0x0040  0xFFFFFFFF  (in a read context only)
//         I2OOBP   0x0044  0xFFFFFFFF  (in a read context only)
//         I2OIBP   0x0048  0xFFFFFFFF  (in a read context only)
//         I2OOBF   0x004C  0xFFFFFFFF  (in a read context only)
	//TPMxSleepEx(5000, 0);
	SleepEx(250, 0);

	DWORD dwReadMem;

//  __BBX Add check for DMA Arb bits L and P, bits 9 and 8
	dwReadMem = *(DWORD*)(dwBarBase+ADDR_DMACTL);
	dwReadMem = dwReadMem & 0xFFFFFFFC;  // __BBX Mask off PI and W
//	printf("DMACTL=%08x\n", dwReadMem);
	if(dwReadMem != 0x00000000)
		returnCode++;
//  __BBX Update for Rev B add arbitration utility flag check
	dwReadMem = *(DWORD*)(dwBarBase+ADDR_ARBUTIL);
//	printf("ARBUTIL=%08x\n", dwReadMem);
	if(dwReadMem != 0x00000000)
		returnCode++;

	dwReadMem = *(DWORD*)(dwBarBase+ADDR_HCTL);
//	printf("HCTL=%08x\n", dwReadMem);
	if(dwReadMem != 0x00000001)
		returnCode++;
	dwReadMem = *(DWORD*)(dwBarBase+ADDR_HINT);
//	printf("HINT=%08x\n", dwReadMem);
	if(dwReadMem != 0x00000000)
		returnCode++;
	dwReadMem = *(DWORD*)(dwBarBase+ADDR_LINT);
//	printf("LINT=%08x\n", dwReadMem);
	if(dwReadMem != 0x00000000)
		returnCode++;
//	__BBX  Not applicable here since not effected by soft reset (HCTL[1])
//	dwReadMem = *(DWORD*)(dwBarBase+ADDR_LBUSCFG);
//	printf("LBUSCFG=%08x\n", dwReadMem);
//	if(dwReadMem != 0x00010B50)
//		returnCode++;

	dwReadMem = *(DWORD*)(dwBarBase+ADDR_I2OHISR);
//	printf("I2OHISR=%08x\n", dwReadMem);
	if(dwReadMem != 0x00000000)
		returnCode++;
	dwReadMem = *(DWORD*)(dwBarBase+ADDR_I2OHIMR);
//	printf("I2OHIMR=%08x\n", dwReadMem);
	if(dwReadMem != 0xFFFFFFFF)
		returnCode++;
	dwReadMem = *(DWORD*)(dwBarBase+ADDR_I2OLISR);
//	printf("I2OLISR=%08x\n", dwReadMem);
	if(dwReadMem != 0x00000000)
		returnCode++;
	dwReadMem = *(DWORD*)(dwBarBase+ADDR_I2OLIMR);
//	printf("I2OLIMR=%08x\n", dwReadMem);