testutil.cpp

一个amccs5933芯片的驱动程序开发源程序和部分文档

	{
		nEepromContMatch = 0;
		printf("  <== Possible error.");
	}
	printf("\n");


// Check the data fields that are transferred to the Operations Registers

// _BBX Update for Rev B, LBUSCFG was 16 bits, now 21 bits
	readLocal(comemID, dwReadMem, (DWORD)0x4FC, 1);
	printf("LocalBusConfig    %02x%02x%02x    %02x%02x%02x", 
		*((UCHAR*)dwReadMem+2), *((UCHAR*)dwReadMem+1), *((UCHAR*)dwReadMem+0), 
		temp[0x6E], temp[0x6D], temp[0x6C]);
	if(memcmp(&temp[0x6C], (UCHAR*)dwReadMem, 3))
	{	nEepromContMatch = 0;
		printf("  <== Possible error.");
	}
	printf("\n");

// _BBX add check of HCTL, bit 0
	readLocal(comemID, dwReadMem, (DWORD)0x4E0, 1);
	HostControlBit = (*((UCHAR*)dwReadMem) & 0x1);  // Get Bit 0 of the Host Control Register
	EEPROMCntrlBit = (temp[0x74] & 0x1);            // Get the EEPROM Host Control Bit
	printf("HostControlBit         %01x         %01x", HostControlBit, EEPROMCntrlBit);
	if(HostControlBit != EEPROMCntrlBit)
	{	nEepromContMatch = 0;
		printf("  <== Possible error.");
	}
	printf("\n");


// Error Report

	if(nEepromContMatch)
		printf("OK: current EEPROM contents match what is within the PCI-DP\n\n");
	else
	{
		printf("WARNING: current EEPROM contents DO NOT match what is within the PCI-DP\n");
		printf("At least one of the following must be true:\n");
		printf("1.) PCI-DP initialization from EEPROM contents failed.\n");
		printf("2.) Some PCI-DP parameters can be modified other than by PCI-DP initialization\n");
		printf("    Therefore, there may be no problem with the check.  The parameters that can\n");
		printf("    be altered other than by the PCI-DP EEPROM initialization sequence are:\n");
		printf("       MasterEnableBit via access to the PCI-DP's PCI interface;\n");
		printf("       LocalBusConfig via access to either of the PCI-DP's interfaces, local or PCI;\n");
		printf("       HostControlBit via access to either of the PCI-DP's interfaces, local or PCI.\n");
	}

}
// Init EEPROM
// Warning!!!  Vendor ID and Device ID must be set to the defaults, else driver 
// will not recognize device.
// Alternately, use your own VendorID and DeviceID, then follow instructions in FAQ
//   to force driver to match up with your 'new device'.

// __BBX Update for longer LocBusCFG word for Rev B
// void initEEPROM (DWORD comemID, USHORT m_usCBoxLocBusCfg, UCHAR m_ucResHold,
void initEEPROM (DWORD comemID, UINT m_usCBoxLocBusCfg, UCHAR m_ucResHold,
  USHORT m_usVenID, USHORT m_usDevID, USHORT m_usSubSysVenID, USHORT m_usSubSysDevID,
  USHORT m_usRevisionID, USHORT m_usMaxLat, USHORT m_usMinGnt, UINT m_uiClassCode, USHORT m_usIntPin)
{
    DWORD returnCode;
    unsigned char temp[EEPROMsize];
    unsigned char temp1[EEPROMsize];
	int nEepromContMatch = 1;
	int errorCnt = 0;

	// Default to zero...
	for (int i = 0 ; i < EEPROMsize ; i++)
		temp[i] = 0 ; 

	// ... then fill in the exceptions.
//	temp[0x40] = 0x37;
//	temp[0x41] = 0x48;
	temp[0x42] = 0x37;	// Pattern required for 3042 to recognize EEPROM for Auto-Configuration
	temp[0x43] = 0x48;

						// See warning above!!!
//	temp[0x44] = 0xbe;	// VendorID
//	temp[0x45] = 0x12;
	temp[0x44] = (UCHAR)m_usVenID;	// VendorID
	temp[0x45] = m_usVenID >> 8;

//	temp[0x46] = 0x42;  // DeviceID
//	temp[0x47] = 0x30;
	temp[0x46] = (UCHAR)m_usDevID;  // DeviceID
	temp[0x47] = m_usDevID >> 8;;


//	temp[0x48] = 0x01;  // RevisionID
	temp[0x48] = (UCHAR)m_usRevisionID;  // RevisionID

//	temp[0x49] = 0x01;	// Class Code = I2O class, I2O subclass, interface = Interrupt
//	temp[0x4a] = 0x00;
//	temp[0x4b] = 0x0e;
	temp[0x49] = (UCHAR)m_uiClassCode;	// Class Code = I2O class, I2O subclass, interface = Interrupt
	temp[0x4a] = (UCHAR)(m_uiClassCode >> 8);
	temp[0x4b] = (UCHAR)(m_uiClassCode >> 16);


	temp[0x4c] = (UCHAR)m_usSubSysVenID;  // Subsystem Vendor ID
	temp[0x4d] = m_usSubSysVenID >> 8;

	temp[0x4e] = (UCHAR)m_usSubSysDevID;  // Subsystem ID
	temp[0x4f] = m_usSubSysDevID >> 8;

//	temp[0x51] = 1; // SHK enable interrupts
	temp[0x51] = (UCHAR)m_usIntPin; // Interrupt Pin

	temp[0x52] = (UCHAR)m_usMinGnt; // MinGnt
	temp[0x53] = (UCHAR)m_usMaxLat; // MaxLat

	temp[0x6C] = (UCHAR)m_usCBoxLocBusCfg; // Local Bus Config
	temp[0x6D] = (UCHAR)(m_usCBoxLocBusCfg >> 8);  // __BBX Update for Rev B
	temp[0x6E] = (UCHAR)(m_usCBoxLocBusCfg >> 16);  // __BBX Update for Rev B

	temp[0x74] = m_ucResHold;

	callWriteEeprom (0, &temp[0], EEPROMsize, comemID);

	memset(temp1, 0x0, sizeof(temp1));
	returnCode = callReadEeprom (0, &temp1[0], EEPROMsize, comemID); // Read contents.
	for (i = 0 ; i < EEPROMsize ; i++)
		if (temp[i] != temp1[i])
			errorCnt++;

	if(errorCnt)
		printf("ERROR: EEPROM contents DO NOT match what was programmed; write failed\n");
	else
		printf("OK: EEPROM programmed OK\n");
}


//
// testEEPROM: Test EEPROM by read and writing values.
// 1. Read original contents.
// 2. Write address pattern test data.
// 3. Read and check address test data.
// 4. Restore original contents.
// 5. Check that restore was successful.
//
DWORD testEEPROM (DWORD comemID)
{
	printf ("Testing EEPROM...\n");

    DWORD returnCode;
    UCHAR temp[EEPROMsize], orig[EEPROMsize], temp2[EEPROMsize];
	int errorCnt = 0;
	DWORD TSTblockSZ = EEPROMsize;
    DWORD i;

	printf ("EEPROM Reads/Writes can take up to 30 seconds.\n");
	printf ("Please wait for tests to complete.\n");
	
	memset(orig, 0x0, sizeof(orig));
	returnCode = callReadEeprom (0, &orig[0], TSTblockSZ, comemID); // Read original contents.
	if (returnCode != NO_ERROR) errorCnt++;

	for (i = 0 ; i < EEPROMsize ; i++) // Init address pattern.
		temp[i] = (UCHAR)i ; 

	returnCode = callWriteEeprom (0, &temp[0], TSTblockSZ, comemID); // Write address test pattern
	if (returnCode != NO_ERROR) errorCnt++;

	memset(temp2, 0x0, EEPROMsize);
	returnCode = callReadEeprom (0, &temp2[0], TSTblockSZ, comemID); // Read.
	if (returnCode != NO_ERROR) errorCnt++;

	for (i = 0 ; i < TSTblockSZ ; i++) // Check address pattern.
		if (temp2[i] != i)
			errorCnt++;

	returnCode = callWriteEeprom (0, &orig[0], TSTblockSZ, comemID); // Restore original contents.
	if (returnCode != NO_ERROR) errorCnt++;

	memset(temp, 0x0, EEPROMsize);
	returnCode = callReadEeprom (0, &temp[0], TSTblockSZ, comemID); // Read.
	if (returnCode != NO_ERROR) errorCnt++;

	for (i = 0 ; i < TSTblockSZ ; i++)
	{ // Check that restore was successful.
		if (temp[i] != orig[i])
		{
			if(errorCnt++ < 8) // only report first 8 errors
			{
				printf ("Error: Read=%08x Original=%08x\n", temp[i], orig[i]);
			}
		}
	}
		
	return (errorCnt);
}


// Memory Test: Write Ones and Zeros
//   1. Host writes all ones to all of shared memory.
//   2. Host reads all of shared memory, confirming data
//   3. Host writes all zeros to all of shared memory.
//   4. Host reads all of shared memory, confirming data

DWORD testMemOneZero(DWORD SMtstBlkBase, DWORD SMoffset, DWORD SMtstBlkSz)
{ // Test Byte Enables.
	DWORD i, dRead, dWrote;
	DWORD errCnt = 0;

	for (i = 0; i < SMtstBlkSz/4; i++)		// Write ones
		((long *) SMtstBlkBase + SMoffset)[i] = -1;
	for (i = 0; i < SMtstBlkSz/4; i++)		// Read and check ones
	{
		dWrote = -1;
		if ( (dRead = ((long *) SMtstBlkBase + SMoffset)[i]) != dWrote)
		{
			if(errCnt++ < 8) // only report first 8 errors
			{
				printf ("Error: Addr=%08x Wrote=%08x Read=%08x\n", 
					(long *) SMtstBlkBase+SMoffset+i, dWrote, dRead);
			}
		}
	}

	for (i = 0; i < SMtstBlkSz/4; i++)		// Write zeroes
		((long *) SMtstBlkBase + SMoffset)[i] = 0;
	for (i = 0; i < SMtstBlkSz/4; i++)		// Read and check zeroes
	{
		dWrote = 0;
		if ( (dRead = ((long *) SMtstBlkBase + SMoffset)[i]) != dWrote)
		{
			if(errCnt++ < 8) // only report first 8 errors
			{
				printf ("Error: Addr=%08x Wrote=%08x Read=%08x\n", 
					(long *) SMtstBlkBase+SMoffset+i, dWrote, dRead);
			}
		}
	}

	return(errCnt);
}

// Memory Test: Write Address test
//   1. Host writes a unique value (the address) to each dword.
//   2. Host reads each dword of the memory, confirming data.
DWORD testMemAddr(DWORD SMtstBlkBase, DWORD SMoffset, DWORD SMtstBlkSz)
{ // Test Memory by writing address pattern.
	DWORD i, dRead, dWrote;
	DWORD errCnt = 0;

	// NOTE: Shared memory address space is known to be 4K DWORDS
	// so address pattern is repeated in 3 byte blocks
	for (i = 0; i < SMtstBlkSz/4; i++)		// Write address pattern
		((long *) SMtstBlkBase + SMoffset)[i] = (i | (i << 12) | (i << 24));

	for (i = 0; i < SMtstBlkSz/4; i++)		// Read and check address pattern
	{
		dWrote = (i | (i << 12) | (i << 24));
		if ( (dRead = ((long *) SMtstBlkBase + SMoffset)[i]) != dWrote)
		{
			if(errCnt++ < 8) // only report first 8 errors
			{
				printf ("Error: PCIAddr=%08x LocalAddr=%08x Wrote=%08x Read=%08x\n", 
					(long *) SMtstBlkBase+SMoffset+i, i*4, dWrote, dRead);
			}
		}
	}
	return(errCnt);
}

// Memory Test: Write Address Complement test
//   1. Host writes complement of unique value (the address) to each dword.
//   2. Host reads each dword of the memory, confirming data.
DWORD testMemAddrComp(DWORD SMtstBlkBase, DWORD SMoffset, DWORD SMtstBlkSz)
{ // Test Address Complement Pattern.
	DWORD i, dRead, dWrote;
	DWORD errCnt = 0;

	// NOTE: Shared memory address space is known to be 4K DWORDS
	// so address pattern is repeated in 3 byte blocks
	for (i = 0; i < SMtstBlkSz/4; i++)		// Write address complment pattern
		((long *) SMtstBlkBase + SMoffset)[i] = ~(i | (i << 12) | (i << 24));

	for (i = 0; i < SMtstBlkSz/4; i++)		// Read and check address complement pattern
	{
		dWrote = ~(i | (i << 12) | (i << 24));
		if ( (dRead = ((long *) SMtstBlkBase + SMoffset)[i]) != dWrote)
		{
			if(errCnt++ < 8) // only report first 8 errors
			{
				printf ("Error: PCIAddr=%08x LocalAddr=%08x Wrote=%08x Read=%08x\n", 
					(long *) SMtstBlkBase+SMoffset+i, i*4, dWrote, dRead);
			}
		}
	}
	return(errCnt);
}

// Memory Test: Write Bytes Test
//   1. Host writes all zeros to all of shared memory.
//   2. Host reads all of shared memory.
//   3. Host confirms data.
//   4. Create wrap-around byte data counter that counts from 1 to 255, never 0 (dWrote).
//   5. Create dword address counter that covers all of shared memory, 0 to 4095 (pdwAddr).
//   6. Host writes byte counter data to byte 0 of dword counter address of memory (nByteOffs).
//   7. Host increments byte data counter and increments dword address counter.
//   8. Host writes byte counter data to byte 1 of dword counter address of memory.
//   9. Host increments byte data counter and increments dword address counter.
//  10. Host writes byte counter data to byte 2 of dword counter address of memory.
//  11. Host increments byte data counter and increments dword address counter.
//  12. Host writes byte counter data to byte 3 of dword counter address of memory.
//  13. Host increments byte data counter and increments dword address counter.
//  14. Repeat pattern of steps 4 to 13 until all dwords of shared memory are 
//      accessed, but restart at the step after the step of the previous loop; 
//      e.g., on second loop through, start at step 8, and then run steps 9 to 13, 
//      and then 6 and 7 to end the second loop.
//		This procedure introduces a "slip" in the byte access pattern (i.e. the
//		first byte is accessed first, then the secend byte is accessed first, etc.).
//  15. Host reads all of shared memory.
//  16. Host confirms data; confirm only the one appropriate byte of each 
//      dword is non-zero and it is the correct value.
//
DWORD testMemWriteBytes(DWORD SMtstBlkBase, DWORD SMoffset, DWORD SMtstBlkSz)
{ // Test Byte Enables.
	DWORD dir;
	DWORD i;
	BYTE dRead, dWrote;
	BYTE nByteOffs;
	DWORD errCnt = 0;
	DWORD nMaxCnt = SMtstBlkSz/4; // Cont in DWORDs
	DWORD dwActRead; 
	DWORD dwExpRead;

	DWORD* pdwAddr = (DWORD*)(SMtstBlkBase + SMoffset*4);
	BYTE* pAddr;

  // Must zero memory for this test to be valid.
  for (i = 0; i < SMtstBlkSz/4; i++)		// Write zeroes
	((long *) SMtstBlkBase + SMoffset)[i] = 0L;
  for (i = 0; i < SMtstBlkSz/4; i++)		// Read zeroes
	if( ((long *) SMtstBlkBase + SMoffset)[i] ) // Check data
		if(errCnt++ < 8)
			printf ("Error: PCIAddr=%08x Wrote=%08x Read=%08x\n", (DWORD)(pdwAddr+i), 0, ((long *) SMtstBlkBase + SMoffset)[i]);

  for(dir=0; dir<2; dir++)
  { // do Write (dir=0) then read (dir=1)
	dWrote = 0;
	nByteOffs = 0;
	for (i = 0; i < nMaxCnt; i++)
	{ // Write Words
		pAddr = (BYTE*)((DWORD*)(pdwAddr+i));
		dWrote++;
		if(dWrote == 0)
			dWrote = 1; // wrap around and skip 0
		if(!dir)
		  *(pAddr+(nByteOffs%4)) = dWrote;
		else
		{
			//dRead = *(pAddr+(nByteOffs%4));
			dRead = dWrote;
			dwActRead = *((DWORD*)(pdwAddr+i));     // read whole DWORDs 
			// NOTE: The following is Endian Dependant! 
			// For Motorola, change to dwExpRead = bRead << (8*(3-(nByteOffs%4)));
			dwExpRead = dRead << (8*(nByteOffs%4)); // to verify single bytes
			if((dwActRead) != (dwExpRead))          // ONLY 1 byte should have value
				if(errCnt++ < 8)
					printf ("Error: PCIAddr=%08x Wrote=%08x Read=%08x\n", (DWORD)(pdwAddr+i), dwExpRead, dwActRead);
		}
	    nByteOffs++; // access next byte
	    if(!((i+1)%4)) 
			nByteOffs++; // incr 1 extra time for each 4 words to change pattern of access
	}
  }
  return(errCnt);
}

//
// Memory Test for AN3042.
// Get pointer to shared memory, offset, and size, then run a series of tests.
//
DWORD testSharedMem (DWORD comemID)
{
	DWORD errorCnt = 0;

	printf ("Testing Memory...\n");
	_flushall();

    // Get a pointer to the Shared Memory area (BAR 0)
    DWORD linBAR[COMEM_MAX_BARS];