📄 comemlif.h
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//////////////////////////////////////////////////////////////////////
//
// File: comemL_if.h
//
// $Archive: /ComemL/Host/Perf42/ComemLif.h $
//
// Copyright (c) 1997 Anchor Chips, Inc. May not be reproduced without
// permission. See the license agreement for more details.
//
//////////////////////////////////////////////////////////////////////
#pragma once
#include "utils.h"
#define ONE_K 1024
#define ONE_MEG (ONE_K * ONE_K)
const int PC_ALLOCATION_MAX_SIZE = 16 * ONE_MEG;
const int PC_ALLOCATION_MIN_SIZE = 4 * ONE_K;
// Macro to create a range of 000111110000.
// Example -- ONES_RANGE32(15, 8) == 00...001111111100000000.
#define ONES_RANGE32(hi,lo) ((0xffffffff >> (31-(hi))) & ~(0xffffffff >> (32-(lo))) )
const DWORD CHECK_MASK_POWER2 = (DWORD) -2;
#define CACHE_REGION_ADDR_MASK ONES_RANGE32(23,9)
#define CACHE_REGION_SIZE_MASK ONES_RANGE32(31,9)
const DWORD CACHE_REGION_MAX_ADDR = 1 << 24;
const DWORD CACHE_REGION_MAX_SIZE = 1 << 23;
const DWORD CACHE_REGION_MIN_SIZE = 1 << 10;
const DWORD CACHE_REGION_FLUSH_VAL = (1 << 7);
const DWORD CACHE_REGION_HARDWARE = (0 << 1);
const DWORD CACHE_REGION_RW_PROG = (1 << 1);
const DWORD CACHE_REGION_RO_PROG = (2 << 1);
const DWORD CACHE_REGION_RW_DATA = (3 << 1);
const DWORD CACHE_REGION_OFF = (0);
const DWORD CACHE_REGION_ON = (1);
////////////////////////////////////////////////////////////////////////
//
// The xlate 2 chip array is used to translate a value received in the drop-down
// list into a value that is suitable for the chip. This is necessary because the list
// is numbered linearly, while the chip is generally 0=off, 1+code=on, so it is non-linear.
// example:
// writeComemL(addr, CACHE_REGION_XLATE2CHIP[list_value], comemID)
#ifdef __cplusplus
const DWORD CACHE_REGION_XLATE2CHIP[] =
{ CACHE_REGION_OFF, // UNUSED
CACHE_REGION_ON + CACHE_REGION_RW_PROG, // RW_PROG
CACHE_REGION_ON + CACHE_REGION_RO_PROG, // RO_PROG
CACHE_REGION_ON + CACHE_REGION_RW_DATA, // RW_DATA
CACHE_REGION_ON + CACHE_REGION_HARDWARE // HARDWARE
};
#endif
#define CS_REGION_SIZE_MASK ONES_RANGE32(31,10)
#define CS_REGION_ADDR_MASK ONES_RANGE32(23,10)
const DWORD CS_REGION_MAX_ADDR = 1 << 24;
const DWORD CS_REGION_MAX_SIZE = 1 << 20;
const DWORD CS_REGION_MIN_SIZE = ONE_K;
// Values used by the chip
const DWORD CS_REGION_OFF = 0;
const DWORD CS_REGION_RDY_COUNT0 = 1;
const DWORD CS_REGION_RDY_INPUT = 2;
const DWORD CS_RDY_COUNT_POSITION = 2; // location of count in bit positions
const DWORD CS_RDY_COUNT_MAX = 16;
#ifdef __cplusplus
const DWORD CS_REGION_XLATE2CHIP[] =
{
CS_REGION_OFF,
CS_REGION_RDY_INPUT,
CS_REGION_RDY_COUNT0
};
const DWORD CS_REGION_XLATE2WIN[] =
{
0, 2+(0), 1, 0,
0, 2+(1), 1, 0,
0, 2+(2), 1, 0,
0, 2+(3), 1, 0,
0, 2+(4), 1, 0,
0, 2+(5), 1, 0,
0, 2+(6), 1, 0,
0, 2+(7), 1, 0,
0, 2+(8), 1, 0,
0, 2+(9), 1, 0,
0, 2+(10),1, 0,
0, 2+(11),1, 0,
0, 2+(12),1, 0,
0, 2+(13),1, 0,
0, 2+(14),1, 0,
0, 2+(15),1, 0,
0, 2+(16),1, 0,
0, 2+(17),1, 0,
0, 2+(18),1, 0,
0, 2+(19),1, 0,
0, 2+(20),1, 0,
0, 2+(21),1, 0,
0, 2+(22),1, 0,
0, 2+(23),1, 0,
0, 2+(24),1, 0,
0, 2+(25),1, 0,
0, 2+(26),1, 0,
0, 2+(27),1, 0,
0, 2+(28),1, 0,
0, 2+(29),1, 0,
0, 2+(30),1, 0,
0, 2+(31),1, 0
};
#endif
const int ADDR_PHYSBASE = 0;
const int ADDR_ADDIN_SIZE = 4;
const int ADDR_HOSTBASE = 0;
const int ADDR_ADDINBASE = 8;
const int ADDR_MEMBASE0 = 0x00;
const int ADDR_MEMSIZE0 = 0x04;
const int ADDR_MEMBASE1 = 0x10;
const int ADDR_MEMSIZE1 = 0x14;
const int ADDR_MEMBASE2 = 0x20;
const int ADDR_MEMSIZE2 = 0x24;
const int ADDR_MEMBASE3 = 0x30;
const int ADDR_MEMSIZE3 = 0x34;
const int ADDR_CSBASE0 = 0x40;
const int ADDR_CSSIZE0 = 0x44;
const int ADDR_CSBASE1 = 0x50;
const int ADDR_CSSIZE1 = 0x54;
const int ADDR_DASIZE = 0x64;
const int ADDR_DALBASE = 0x68;
const int ADDR_NFCMD = 0x70;
const int ADDR_HMBASE = 0x80;
const int ADDR_HMSIZE = 0x84;
const int ADDR_PFADDR = 0x88;
const int ADDR_OPSBASE = 0x90;
const int ADDR_LCTL = 0xf0;
// TPM: modified for 3042
const int ADDR_I2OHISR = 0x030;
const int ADDR_I2OHIMR = 0x034;
const int ADDR_I2OLISR = 0x038;
const int ADDR_I2OLIMR = 0x03C;
const int ADDR_I2OIBP = 0x040;
const int ADDR_I2OIBF = 0x044;
const int ADDR_I2OOBP = 0x048;
const int ADDR_I2OOBF = 0x04C;
const int ADDR_DAHBASE = 0x460;
const int ADDR_NVCMD = 0x4a0;
const int ADDR_NVREAD = 0x4a4;
const int ADDR_NVSTAT = 0x4a8;
const int ADDR_DMALBASE= 0x4B0;
const int ADDR_DMAHBASE= 0x4B4;
const int ADDR_DMASIZE = 0x4B8;
const int ADDR_DMACTL = 0x4BC;
const int ADDR_HCTL = 0x4e0;
const int ADDR_HINT = 0x4e4;
const int ADDR_HLDATA = 0x4e8;
const int ADDR_LINT = 0x4f4;
const int ADDR_LHDATA = 0x4f8;
const int ADDR_LBUSCFG = 0x4fC;
#define DA_HOST_ADDR_MASK ONES_RANGE32(31,10)
#define DA_HOST_MIN_ADDR ( 1 << 10)
#define DA_ADDIN_ADDR_MASK ONES_RANGE32(23,10)
#define DA_REGION_SIZE_MASK ONES_RANGE32(31,10)
#define DA_REGION_MAX_HOST_ADDR ( -1) /* no max */
#define DA_REGION_MAX_ADDIN_ADDR ( 1 << 24)
#define DA_REGION_MAX_SIZE ( 1 << 20)
#define DA_REGION_MIN_SIZE ( ONE_K)
#define DA_REGION_OFF ( 0)
#define DA_REGION_ON ( 1)
#define DA_REGION_CYCLE_SPECIAL ( (0 << 1) + DA_REGION_ON)
#define DA_REGION_CYCLE_IO ( (1 << 1) + DA_REGION_ON)
#define DA_REGION_CYCLE_MEM ( (2 << 1) + DA_REGION_ON)
#define DA_REGION_CYCLE_CONFIG ( (3 << 1) + DA_REGION_ON)
#ifdef __cplusplus
const int DA_REGION_XLATE2CHIP[] =
{
DA_REGION_OFF,
DA_REGION_CYCLE_SPECIAL,
DA_REGION_CYCLE_IO,
DA_REGION_CYCLE_MEM,
DA_REGION_CYCLE_CONFIG
};
#endif
#define OPS_REG_ADDR_MASK ONES_RANGE32(23,11)
#define OPS_REG_REGION_MAX_ADDR ( 1 << 24)
#define OPS_REG_REGION_MIN_SIZE ( 0x800)
#ifdef __cplusplus
const int OPS_REG_REGION_XLATE2CHIP[] = { 0, 1, 3};
const int OPS_REG_REGION_XLATE2WIN[] = { 0, 1, 2, 2};
#endif
#define PCI_PAGE_TABLE_ENABLE ( 1)
#define PCI_PAGE_TABLE_DISANABLE ( 0)
//////////////////////////////////////////////////////////////////////
// EEPROM related values
//////////////////////////////////////////////////////////////////////
#define MAX_EEPROM_ADDR ( 0x800)
#define EEPROM_ADDR_MASK ( 0x700)
#define EEPROM_WRITE_ENABLE ( 0)
#define EEPROM_4READ_ENABLE ( 3 )
#define SERIAL_REG2_DONE_BIT ( 1)
#define SERIAL_WRITE_ACK_MASK ( 0xe0)
#define SERIAL_READ_ACK_MASK ( 0xe0)
#define EEPROM_WRITE ( 0)
#define EEPROM_READ ( 1)
typedef struct _comem_opsregs_struct
{
unsigned long membase0; // 0x00
unsigned long memsize0;
unsigned long unused_08;
unsigned long unused_0c;
unsigned long membase1; // 0x10
unsigned long memsize1;
unsigned long unused_18;
unsigned long unused_1c;
unsigned long membase2; // 0x20
unsigned long memsize2;
unsigned long unused_28;
unsigned long unused_2c;
unsigned long membase3; // 0x30
unsigned long memsize3;
unsigned long unused_38;
unsigned long unused_3c;
unsigned long csbase0; // 0x40
unsigned long cssize0;
unsigned long unused_48;
unsigned long unused_4c;
unsigned long csbase1; // 0x50
unsigned long cssize1;
unsigned long unused_58;
unsigned long unused_5c;
unsigned long dahbase; // 0x60
unsigned long dasize;
unsigned long dalbase;
unsigned long unused_6c;
unsigned long nfcmd; // 0x70
unsigned long unused_74;
unsigned long unused_78;
unsigned long unused_7c;
unsigned long hmbase; // 0x80
unsigned long hmsize;
unsigned long pfaddr;
unsigned long unused_8;
unsigned long opsbase; // 0x90
unsigned long unused_94;
unsigned long unused_98;
unsigned long unused_9c;
unsigned long nvcmd; // 0xa0
unsigned long nvread;
unsigned long nvstat;
unsigned long unused_ac;
unsigned long unused_b0; // 0xb0
unsigned long unused_b4;
unsigned long unused_b8;
unsigned long unused_bc;
unsigned long unused_c0; // 0xc0
unsigned long unused_c4;
unsigned long unused_c8;
unsigned long unused_cc;
unsigned long unused_d0; // 0xd0
unsigned long unused_d4;
unsigned long unused_d8;
unsigned long unused_dc;
unsigned long hctl; // 0xe0
unsigned long hint;
unsigned long hldata;
unsigned long unused_ec;
unsigned long lctl; // 0xf0
unsigned long lint;
unsigned long lhdata;
unsigned long unused_fc;
} comem_opsregs_struct;
struct nfcmd_struct
{
unsigned long command : 4;
unsigned long dcacheFlag : 1;
unsigned long unused : 4;
unsigned long addr : 15;
unsigned long unused2 : 8;
};
struct hctl_struct
{
unsigned long resetOut : 1;
unsigned long resetOutSoftBit : 1; // added Soft Reset for Comem_B
unsigned long unused : 3;
// unsigned long unused : 4;
unsigned long debug : 3;
unsigned long ifill : 2;
unsigned long dfill : 3;
unsigned long dwrite : 3;
unsigned long unused2 : 16;
};
#define NUM_HINT_INTERRUPTS ( 9)
struct hint_struct
{
unsigned long intType : NUM_HINT_INTERRUPTS;
unsigned long unused : 4;
unsigned long region : 3;
unsigned long intMask : NUM_HINT_INTERRUPTS;
unsigned long unused2 : 16-NUM_HINT_INTERRUPTS;
};
#define HINT_REGION_ACCESS 1
#define HINT_REGION_MISS 2
#define HINT_PAGE_FAULT 4
#define HINT_SW 8
#define HINT_HW 0x10
#define HINT_NAIL_DONE 0x20
#define HINT_FLUSH_DONE 0x40
#define HINT_NF_DONE (HINT_NAIL_DONE | HINT_FLUSH_DONE)
#define HINT_DCACHE_OV 0x80
#define HINT_ICACHE_OV 0x100
#define HINT_TYPE_MASK ONES_RANGE32(NUM_HINT_INTERRUPTS-1, 0)
struct hldata_struct
{
unsigned long data : 16;
unsigned long unused : 8;
unsigned long intOut : 1;
unsigned long unused2 : 7;
};
struct lctl_struct
{
unsigned long mode_486 : 1;
unsigned long unused : 15;
unsigned long unused2 : 16;
};
#define NUM_LINT_INTERRUPTS ( 9)
struct lint_struct
{
unsigned long intType : NUM_LINT_INTERRUPTS;
unsigned long unused : 4;
unsigned long region : 3;
unsigned long intMask : NUM_LINT_INTERRUPTS;
unsigned long unused2 : 16-NUM_LINT_INTERRUPTS;
};
struct lhdata_struct
{
unsigned long data : 16;
unsigned long unused : 8;
unsigned long intOut : 1;
unsigned long unused2 : 7;
};
#define LCTL_486_MODE 1
#ifdef __cplusplus
const comem_opsregs_struct ops;
#define ops_offset(hmsize) ((&ops.hmsize-&ops.membase0) * sizeof(long))
#endif
#define NFCMD_INVALIDATE 8
#define NFCMD_FLUSH 9
#define NFCMD_NAIL_NOFILL 1
#define NFCMD_NONAIL_FILL 2
#define NFCMD_NAIL_FILL 3
#define NFCMD_UNNAIL 4
#define NFCMD_DCACHE 0x10
#define NFCMD_ICACHE 0x00
#define NFCMD_DATA_MASK 0xfffe00
//////////////////////////////////////////////////////////////////////
// VxD related values
//////////////////////////////////////////////////////////////////////
#include "comemdrv.h"
/////////////////////////////////////////////////////////////////////////////
// Vxd Interface functions
DWORD comemOpenDriverL(DWORD comemID);
DWORD comemCloseDriverL(DWORD comemID);
DWORD comemCopyBarPtrL(DWORD linBAR[COMEM_MAX_BARS], DWORD comemID);
DWORD comemGetPCIInfoL(PCI_CONFIG_HEADER_0 *pciPtr, DWORD comemID);
DWORD comemSetPCIInfoL(PCI_CONFIG_HEADER_0 *pciPtr, DWORD comemID);
DWORD comemDestroyLinPtrL(DWORD comemID);
DWORD comemDestroyBarPtrL(DWORD comemID);
DWORD comemAllocContigMemL(DWORD pageCount, DWORD *linearAddr, DWORD *physAddr, DWORD comemID);
DWORD comemDeAllocContigMemL(DWORD *linearAddr, DWORD *physAddr, DWORD comemID);
DWORD comemGetStatusL(DWORD *refCount, DWORD comemID);
DWORD comemCreateBarPtrL(DWORD linBAR[COMEM_MAX_BARS], DWORD comemID);
#define OPS ((comem_opsregs_struct *)(comemDevL[comemID]->linBAR[1]))
enum errcodeE fake_write(DWORD addr, DWORD data, DWORD comemID);
#ifdef __cplusplus
const int COLUMN_PRIORITY = 0;
const int COLUMN_UPROC_START = 1;
const int COLUMN_UPROC_BLOCK = 2;
const int COLUMN_TYPE = 3;
const int COLUMN_ALLOCATION = 4;
const int ROW_OPS_REG = 0;
const int ROW_DA = 1;
const int ROW_CS = 2;
const int ROW_CACHE = 3;
inline int getRowType(int row)
{
switch (row)
{
case 0:
return ROW_OPS_REG;
case 1:
return ROW_DA;
case 2:
case 3:
return ROW_CS;
case 4:
case 5:
case 6:
case 7:
return ROW_CACHE;
default:
report_error("Bad row %d passed to getRowType.", row);
return 0;
}
}
//static const char *priority[] = {"Ops regs", "Direct Access", "CS-0", "CS-1", "Memory 0", "Memory 1", "Memory 2", "Memory 3", "Unused area" };
static const char *priority[] = {"Ops Region", "Direct Access Region", "CS-0 Region", "CS-1 Region", "Memory 0", "Memory 1", "Memory 2", "Memory 3", "Unused area" };
static const char* cache_type[] = {"disabled", "RW prog", "RO prog", "RW data", "hardware"};
static const char* cs_type[] = {"disabled", "CSx_RDYIN#->ready out",
"0 added wait states", "1 added wait state", "2 added wait states", "3 added wait states",
"4 added wait states", "5 added wait states", "6 added wait states", "7 added wait states",
"8 added wait states", "9 added wait states", "10 added wait states", "11 added wait states",
"12 added wait states", "13 added wait states", "14 added wait states", "15 added wait states"};
static const char* da_type[] = {"disabled", "Int ACK/special", "I/O cycle", "Memory cycle", "Config cycle"};
static const char* ops_reg_type[] = {"No writes", "Limited access", "Full access"};
// spaces in "block size are intended to increase field width in the grid.
static const char* headers[] = {"Region ", "Local Bus Addr", "Block Size ", "Access Type", "PCI Addr "};
extern const char *ini_file_name;
#endif // cplusplus
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