pci_device_init.asm

基于ADSP 的PCI 代码

/* ********************************************************************************
 * 
 * Copyright (c) 2003 Analog Devices Inc.  All rights reserved.
 *
 *
 * PCI module initialization in device mode
 *
 * The window sizes (memory and I/O) can be changed by modifying
 * PCI_MEM_SIZE & PCI_IO_SIZE in VisualDSP\Blackfin\include\defBF535.h
 *
 *
 ***********************************************************************************/

#include "defBF535.h"
#include "pci_ids.h"
#include "My_Header.h"

.global pci_cfg_init;

.section program;

/**********************  PCI module Configuration ****************************/
pci_cfg_init:
  
Initialize:
  	P4.H = HI(PCI_STAT); P4.L= LO(PCI_STAT);		
  	R1 = [P4];
  	[P4] = R1;  // Clear PCI status register 
  	SSYNC;

  	P4.H = HI(PCI_CTL); P4.L= LO(PCI_CTL);	 
  	R0.H = 0x0; R0.L = 0x0;
  	[P4] = R0;     // disable PCI before writing config space
  	SSYNC;

  	P4.H = HI(PCI_ICTL); P4.L= LO(PCI_ICTL);		
  	R0.H = 0x0; R0.L = 0x0;
  	[P4] = R0;     // clear PCI interrupt enables before writing config space
  	SSYNC;

/*************** BEGIN INITIALIZATION ***************************/
Vendor_ID:	
  	P4.H = HI(PCI_CFG_VIC); P4.L = LO(PCI_CFG_VIC);
  	R0.H = 0x0; R0.L = PCI_VENDOR_ID;
  	[P4] = R0;     // write PCI_CFG_VIC
  	SSYNC;

Device_ID:	
  	P4.H = HI(PCI_CFG_DIC); P4.L= LO(PCI_CFG_DIC);
  	R0.H = 0x0; R0.L = PCI_DEVICE_ID;
  	[P4] = R0;     // write PCI_CFG_DIC
  	SSYNC;


/** in Device mode this register should be written by the system host
	in this example however, I will at least enable bus mastership **/
Command:	
  	P4.H = HI(PCI_CFG_CMD); P4.L = LO(PCI_CFG_CMD);
  	R0.H = 0x0; R0.L = 0x4;
  	[P4] = R0;     
  	SSYNC;

Revision_ID:	
  	P4.H = HI(PCI_CFG_RID); P4.L = LO(PCI_CFG_RID);
  	R0.H = 0x0; R0.L = PCI_REVISION_ID;
  	[P4] = R0;     
  	SSYNC;

Class_Code:	
  	P4.H = HI(PCI_CFG_CC); P4.L = LO(PCI_CFG_CC);
  	R0.H = PCI_BASE_CLASS_SIGNAL_PROCESSING; R0.L = PCI_CLASS; 
  	[P4] = R0;     
  	SSYNC;

// This function is not supported on the ADSP-BF535
Cache_Line_Size:
  	P4.H = HI(PCI_CFG_CLS); P4.L = LO(PCI_CFG_CLS);
  	R0.H = 0x0; R0.L = 0x0;
  	[P4] = R0;     
  	SSYNC;

// in Device mode this register should be written by the system host
Latency_Timer:
	P4.H = HI(PCI_CFG_MLT); P4.L = LO(PCI_CFG_MLT);
  	R0 = 0x0; 
  	[P4] = R0;     
  	SSYNC;

Header_Type:
  	P4.H = HI(PCI_CFG_HT); P4.L = LO(PCI_CFG_HT);
  	R0.H= 0x0; R0.L = 0x0;
  	[P4] = R0;     // Header Type 0 & Single function device
  	SSYNC;

// This function is not supported on the ADSP-BF535
Built_In_Self_Test:
  	P4.H = HI(PCI_CFG_CLS); P4.L = LO(PCI_CFG_CLS);
  	R0.H= 0x0; R0.L = 0x0;
  	[P4] = R0;     
  	SSYNC;

Subsystem_Vendor_ID:	
  	P4.H = HI(PCI_CFG_SVID); P4.L = LO(PCI_CFG_SVID);
  	R0.H= 0x0; R0.L = 0x0;
  	[P4] = R0;     
  	SSYNC;

Subsystem_ID:	
  	P4.H = HI(PCI_CFG_SID); P4.L = LO(PCI_CFG_SID);
  	R0.H= 0x0; R0.L = 0x0;
  	[P4] = R0;     
  	SSYNC;

Interrupt_Pin:	
  	P4.H = HI(PCI_CFG_IP); P4.L = LO(PCI_CFG_IP);
  	R0.H= 0x0;   R0.L = 0x1;	/* INTA is used by ADSP-BF535 in device mode  */
  	[P4] = R0;     
  	SSYNC;

// the host system will provide this information
Interrupt_Line:	
  	P4.H = HI(PCI_CFG_IL); P4.L = LO(PCI_CFG_IL);
  	R0.H= 0x0;   R0.L = 0x0;	
  	[P4] = R0;     
  	SSYNC;

Minimum_Grant:		
  	P4.H = HI(PCI_CFG_MING); P4.L = LO(PCI_CFG_MING);
  	R0.H = 0x0; R0.L = PCI_MIN_GRANT;
  	[P4] = R0;     
  	SSYNC;

Maximum_Latency:		
  	P4.H = HI(PCI_CFG_MAXL); P4.L = LO(PCI_CFG_MAXL);
  	R0.H= 0x0; R0.L = PCI_MAX_LATENCY;
  	[P4] = R0;     
  	SSYNC;

// DMBARM & DIBARM specify the size of memory and I/O requested by the device
Device_Memory_BAR_Mask:		
  	P4.H = HI(PCI_DMBARM); P4.L = LO(PCI_DMBARM);
  	R0.H = HI(PCI_MEM_BARMASK); R0.L = LO(PCI_MEM_BARMASK);
  	[P4] = R0;     // specify the memory size required by the ADSP-BF535 PCI 
  	SSYNC;

Device_IO_BAR_Mask:	
  	P4.H = HI(PCI_DIBARM); P4.L = LO(PCI_DIBARM);
  	R0.H = HI(PCI_IO_BARMASK); R0.L = LO(PCI_IO_BARMASK);
  	[P4] = R0;     // specify the I/O size required by the ADSP-BF535 PCI 
  	SSYNC;


//BF535 specific register to map PCI memory space to the processor's mem space
Target_Memory_Base_Address_Pointer:	
  	P4.H = HI(PCI_TMBAP); P4.L = LO(PCI_TMBAP);
  	R0.H = HI(L2_BASE); R0.L = LO(L2_BASE);
  	//R0 = 0x0; // base of SDRAM
  	[P4] = R0;     //  map inbound memory accesses to the base of L2 memory
  	SSYNC;

//BF535 specific register to map PCI IO space to the processor's MMR space 
Target_IO_Base_Address_Pointer:		
  	P4.H = HI(PCI_TIBAP); P4.L = LO(PCI_TIBAP);
  	R0.H = HI(PCI_CTL); R0.L = LO(PCI_CTL);	
  	[P4] = R0;     // map inbound I/O accesses to 0xFFC0 4000 (PCI MMR space)
  	SSYNC;

/* enable PCI interrupts */
	P4.H = HI(PCI_ICTL); P4.L = LO(PCI_ICTL);
	R0.H= 0x0; R0.L = (PCI_ICTL_RESET);
  	[P4] = R0;     // Enable PCI reset to generate an interrupt to the ADSP-BF535 core
  	SSYNC;

enable_PCI:
	P4.H = HI(PCI_CTL); P4.L = LO(PCI_CTL);
  	R0.H= 0x0; R0.L = (PCI_CTL_ENABPCI | PCI_CTL_FASTBCK2BCK) ;	
  	[P4] = R0;     /* enable PCI as a Device; enable Fast back-to-back*/
  	SSYNC;
pci_cfg_init.end:  rts;  /* Return from PCI init subroutine */