pci_device_init.asm_bak

基于ADSP 的PCI 代码

/***************************************************************************

PCI module initialization in device mode

The window sizes (memory and I/O) can be changed by modifying
PCI_MEM_SIZE & PCI_IO_SIZE in VisualDSP\Blackfin\include\defBF535.h


***************************************************************************/

#include "defBF535.h"
#include "pci_ids.h"

.global pci_cfg_init;

.section program;

/**********************  PCI module Initialization ****************************/
pci_cfg_init:

  P4.H = (PCI_STAT >> 16); P4.L= (PCI_STAT & 0xFFFF);		// clear PCI status before writing config space
  R0 = 0xFFFFFFFF;
  [P4] = R0; 
  SSYNC;

  P4.H = (PCI_CTL >> 16); P4.L= (PCI_CTL & 0xFFFF);		// disable PCI before writing config space
  R0.H= 0x0; R0.L = 0x0;
  [P4] = R0;     // write PCI_CFG_CTL
  SSYNC;

  P4.H = (PCI_ICTL >> 16); P4.L= (PCI_ICTL & 0xFFFF);		// clear PCI interrupt enables before writing config space
  R0.H= 0x0; R0.L = 0x0;
  [P4] = R0;     // write PCI_CFG_ICTL
  SSYNC;


device_id:	
  P4.H = (PCI_CFG_DIC >> 16); P4.L= (PCI_CFG_DIC & 0xFFFF);
  R0.H= 0x0; R0.L = PCI_DEVICE_ID;
  [P4] = R0;     // write PCI_CFG_DIC
  SSYNC;

vendor_id:	
  P4.H = (PCI_CFG_VIC >> 16); P4.L= (PCI_CFG_VIC & 0xFFFF);
  R0.H= 0x0; R0.L = PCI_VENDOR_ID;
  [P4] = R0;     // write PCI_CFG_VIC
  SSYNC;

// Host should write to this register  
command:	
  P4.H = (PCI_CFG_CMD >> 16); P4.L= (PCI_CFG_CMD & 0xFFFF);
  R0.H= 0x0; R0.L = 0x0;
  [P4] = R0;     // write PCI_CFG_CMD
  SSYNC;

header_type:	
  P4.H = (PCI_CFG_HT >> 16); P4.L= (PCI_CFG_HT & 0xFFFF);
  R0.H= 0x0; R0.L = 0x0;
  [P4] = R0;     // write PCI_CFG_HT
  SSYNC;

class_code:	
  P4.H = (PCI_CFG_CC >> 16); P4.L= (PCI_CFG_CC & 0xFFFF);
  R0.H= PCI_BASE_CLASS_SIGNAL_PROCESSING; R0.L = PCI_CLASS; // 2/05/02, : added Base class value of 0x11
  [P4] = R0;     // write PCI_CFG_CC
  SSYNC;

revision_id:	
  P4.H = (PCI_CFG_RID >> 16); P4.L= (PCI_CFG_RID & 0xFFFF);
  R0.H= 0x0; R0.L = PCI_REVISION_ID;
  [P4] = R0;     // write PCI_CFG_RID
  SSYNC;


subsystem_id:	
  P4.H = (PCI_CFG_SID >> 16); P4.L= (PCI_CFG_SID & 0xFFFF);
  R0.H= 0x0; R0.L = 0x0;
  [P4] = R0;     // write PCI_CFG_SID
  SSYNC;

subsystem_vendor_id:	
  P4.H = (PCI_CFG_SVID >> 16); P4.L= (PCI_CFG_SVID & 0xFFFF);
  R0.H= 0x0; R0.L = 0x0;
  [P4] = R0;     // write PCI_CFG_SVID
  SSYNC;

min_grant:		
  P4.H = (PCI_CFG_MING >> 16); P4.L= (PCI_CFG_MING & 0xFFFF);
  R0.H= 0x0; R0.L = PCI_MIN_GRANT;
  [P4] = R0;     // write PCI_CFG_MING
  SSYNC;

max_latency:		
  P4.H = (PCI_CFG_MAXL >> 16); P4.L= (PCI_CFG_MAXL & 0xFFFF);
  R0.H= 0x0; R0.L = PCI_MAX_LATENCY;
  [P4] = R0;     // write PCI_CFG_MAXL
  SSYNC;

dmbarm:		
  P4.H = (PCI_DMBARM >> 16); P4.L= (PCI_DMBARM & 0xFFFF);
  R0.H= (PCI_MEM_BARMASK >> 16); R0.L = (PCI_MEM_BARMASK & 0xFFFF);
  [P4] = R0;     // specify the memory size required by the ADSP-BF535 PCI 
  SSYNC;

  
dibarm:	
  P4.H = (PCI_DIBARM >> 16); P4.L= (PCI_DIBARM & 0xFFFF);
  R0.H= (PCI_IO_BARMASK >> 16); R0.L = (PCI_IO_BARMASK & 0xFFFF);
  [P4] = R0;     // specify the I/O size required by the ADSP-BF535 PCI 
  SSYNC;


//BF535 specific register to map PCI memory space to the processor's mem space
tmbap:	
  P4.H = (PCI_TMBAP >> 16); P4.L= (PCI_TMBAP & 0xFFFF);
  R0.H= (L2_BASE >> 16); R0.L = (L2_BASE & 0xFFFF);
  //R0 = 0x0; // base of SDRAM
  [P4] = R0;     //  map inbound memory accesses to the base of L2 memory
  SSYNC;

//BF535 specific register to map PCI IO space to the processor's MMR space 
tibap:		
  P4.H = (PCI_TIBAP >> 16); P4.L= (PCI_TIBAP & 0xFFFF);
  R0.H= (PCI_CTL >> 16); R0.L = (PCI_CTL & 0xFFFF);	
  [P4] = R0;     // map inbound I/O accesses to 0xFFC0 4000 (PCI MMR space)
  SSYNC;


int_pin:	
  P4.H = (PCI_CFG_IP >> 16); P4.L= (PCI_CFG_IP & 0xFFFF);
  R0.H= 0x0;   R0.L = 0x1;	/* INTA is used by ADSP-BF535 in device mode  */
  [P4] = R0;     // write PCI_CFG_IP
  SSYNC;


enab_pci:
  P4.H = (PCI_ICTL >> 16); P4.L= (PCI_ICTL & 0xFFFF);			/* enable PCI interrupts */
  R0.H= 0x0; R0.L = (PCI_ICTL_RESET);
  [P4] = R0;     // Enable PCI reset to generate an interrupt to the ADSP-BF535 core
  SSYNC;

  P4.H = (PCI_CTL >> 16); P4.L= (PCI_CTL & 0xFFFF);
  R0.H= 0x0; R0.L = (PCI_CTL_ENABPCI | PCI_CTL_FASTBCK2BCK) ;	/* enable PCI as a Device; enable Fast back-to-back*/
  [P4] = R0;     // write PCI_CFG_CTL 
  SSYNC;
  
pci_cfg_init.end:  rts;  /* Return from PCI subroutine */