hawk35_eagle35.asm

基于ADSP 的PCI 代码

/************************************	01/07/03	********************************************
 *	DEVICE (HAWK-35) TO HOST (EAGLE-35) PCI TRANSFER EXAMPLE
 *  The HAWK-35 and EAGLE-35 boards are sold and supported by Momentum Data Systems (MDS) 
 *  Both boards have the ADSP-BF535 processor as the main processor
 *
 *  author: JM
 *  rev.    1.0
 *  date:   7/3/03
 *  software rev. VisualDSP++ 3.1
 *
 *	This program sends a "blink program" or a block of data 
 *  (depending on which file is included in the project, blinkDevHost.asm or buffer_devHost.asm, respectively)
 *  from the DEVICE (HAWK-35) to the base of L2 of the Host (EAGLE-35)	using MemDMA.
 *  To run it on the host reset the PC value to 0xF000 0000.  
 *
 *	
 *************************************************************************************************/
 
 

#include "defBF535.h"
#include "pci_ids.h"
#include "My_Header.h"

 
.section program;
.align 4;
.extern DMA_TO_TARGET;
.extern pci_cfg_init;



// install event handlers
P0.H= HI(EVT7); P0.L = LO(EVT7);
P1.H = PCI_RST_ISR;  p1.l = PCI_RST_ISR;  // PCI ISR
[P0] = P1;	
ssync; 

P0.H= HI(EVT3); P0.L = LO(EVT3);
p1.h = expthand; p1.l = expthand;
[p0] = p1;	// software exception
ssync;

P0.H= HI(EVT5); P0.L = LO(EVT5);
p1.h = hwerrhand; p1.l = hwerrhand;
[p0] = p1;		// hardware exception
ssync;


//Check revision of silicon to set SIC_IMASK appropriately
P3.H = HI(SIC_IMASK);  P3.L = LO(SIC_IMASK);
P0.H = HI(CHIPID);     P0.L = LO(CHIPID);
R0 = [P0];
R1.H = 0XF000;
R1 = R1 & R0;
cc = bittst(r1, 28); // check if CHIP_ID is non zero
if cc jump rev_1_0; // if CHIP_ID is non-zero, a 1 in SIC_MASK enables interrupts

rev0_1_or_0_2:
//Unmask the Interrupt in System Interrupt Mask Register
R6 = [p3];
BITCLR(R6,3); // change bit to desired bit position to match your application
[ P3 ] = R6;
SSYNC;
jump continue;

rev_1_0:
R6 = [p3];
BITSET(R6,3); // change bit to desired bit position to match your application
[ P3 ] = R6;
SSYNC;

continue:
/*  unmask PCI interrupt at the core level. */
P2.H = HI(IMASK); P2.L = LO(IMASK);
R0.l   = W[P2];
R1.L = EVT_IVG7 & 0XFFFF;
R0 = R0 | R1;
W[P2] = R0.l;  /* Set the IVG7 mask bit to unmask the interrupt*/
ssync;

	
  /* set PF15 to be output for LED  */
  P0.H= HI(FIO_DIR); P0.L = LO(FIO_DIR);
  R0.l = w[P0];
  BITSET(R0,15);
  w[P0] = R0.l; /* set PF 15 as an output */
  ssync;

/********* Initialize SDRAM ******************/
call sdram_init;

/********* Initialize PCI interface ***********/
call pci_cfg_init;
   

CALL DMA_TO_TARGET;
 
NOP; // simpy a place for a breakpoint   	

   	IDLE;
   	SSYNC;
   
   /****************************************************************/
	
HERE:
JUMP HERE;	

		
/*
 * Software Exception Handler: lights up LEDs 1-5 and loops forever.
 */
expthand:
  P0.H= 0xffc0; P0.L = 0x2406;     
  r0.h = 0; r0.l = 0xf800;
  r1 = ~r0;
  r1 = r1 & r0;
  W[p0]=r1;
  csync;
  jump expthand;

/*
 * Hardware Exception Handler:	lights up LEDs 1, 3, and 5 and loops forever.
 */
hwerrhand:
  P0.H= 0xffc0; P0.L = 0x2406;     
  r0.h = 0; r0.l = 0xa800;
  r1.h = 0; r1.l = 0xf800;
  r0 = ~r0;
  r1 = r1 & r0;
  W[p0]=r1;
  csync;
  jump hwerrhand;

/* Initialize Micron 64MB MT48LC4M16A2-7E - copied from sdram_init.asm */
sdram_init:
  P0.H= HI(EBIU_SDRRC); P0.L = LO(EBIU_SDRRC);
  r0 = 0x0817 (z);
  W[p0] = r0;
  ssync;

  P0.H= HI(EBIU_SDBCTL); P0.L = LO(EBIU_SDBCTL);
  r0.h = 0x0;  r0.l = 0x0015;
  // r0.l = 0x0001;  // for BUB
  [p0] = r0;
  ssync;

  P0.H= HI(EBIU_SDGCTL); P0.L = LO(EBIU_SDGCTL);
  r0.h = 0x0091; r0.l = 0x99fb;
  [p0] = r0;
  ssync;

  rts;


/**********************************************************************/
.align 4;
PCI_RST_ISR:
  P4.H = HI(PCI_CTL); P4.L = LO(PCI_CTL);		// disable PCI before writing config space
  r0.h = 0x0; r0.l = 0x0;
  [p4] = r0;     // disable PCI
  SSYNC;

  P4.H = HI(PCI_STAT); P4.L = LO(PCI_STAT);		// clear PCI status before writing config space
  r0 = [p4];
  bitset(r0,6);  /*  Write a 1 to clear PCI RESET status bit */
  [p4] = r0; 
  SSYNC;

  P0.H = HI(FIO_FLAG_C); P0.L = LO(FIO_FLAG_C);
  R0.l = w[P0];
  BITSET(R0,15);
  w[P0] = R0.l; /* clear PF 15 */
  ssync;

  call pci_cfg_init;

  P0.H = HI(FIO_FLAG_S); P0.L = LO(FIO_FLAG_S);
  R0.l = w[P0];
  BITSET(R0,15);
  w[P0] = R0.l; /* set PF 15 */
  ssync;

rti; /* return from PCI Reset interrupt */