📄 defblackfin.h
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#define DTEST_DATA1 0xFFE00404 // Data Test Data Register
#define DTEST_DATA2 0xFFE00408 // Data Test Data Register
#define DTEST_DATA3 0xFFE0040C // Data Test Data Register
#define IMEM_CONTROL 0xFFE01004 // Instruction Memory Control
#define ICPLB_STATUS 0xFFE01008 // Instruction Cache miss status
#define ICPLB_FAULT_ADDR 0xFFE0100C // Instruction Cache miss address
#define ICPLB_ADDR0 0xFFE01100 // Instruction Cache Protection Lookaside Buffer 0
#define ICPLB_ADDR1 0xFFE01104 // Instruction Cache Protection Lookaside Buffer 1
#define ICPLB_ADDR2 0xFFE01108 // Instruction Cache Protection Lookaside Buffer 2
#define ICPLB_ADDR3 0xFFE0110C // Instruction Cache Protection Lookaside Buffer 3
#define ICPLB_ADDR4 0xFFE01110 // Instruction Cache Protection Lookaside Buffer 4
#define ICPLB_ADDR5 0xFFE01114 // Instruction Cache Protection Lookaside Buffer 5
#define ICPLB_ADDR6 0xFFE01118 // Instruction Cache Protection Lookaside Buffer 6
#define ICPLB_ADDR7 0xFFE0111C // Instruction Cache Protection Lookaside Buffer 7
#define ICPLB_ADDR8 0xFFE01120 // Instruction Cache Protection Lookaside Buffer 8
#define ICPLB_ADDR9 0xFFE01124 // Instruction Cache Protection Lookaside Buffer 9
#define ICPLB_ADDR10 0xFFE01128 // Instruction Cache Protection Lookaside Buffer 10
#define ICPLB_ADDR11 0xFFE0112C // Instruction Cache Protection Lookaside Buffer 11
#define ICPLB_ADDR12 0xFFE01130 // Instruction Cache Protection Lookaside Buffer 12
#define ICPLB_ADDR13 0xFFE01134 // Instruction Cache Protection Lookaside Buffer 13
#define ICPLB_ADDR14 0xFFE01138 // Instruction Cache Protection Lookaside Buffer 14
#define ICPLB_ADDR15 0xFFE0113C // Instruction Cache Protection Lookaside Buffer 15
#define ICPLB_DATA0 0xFFE01200 // Instruction Cache 0 Status
#define ICPLB_DATA1 0xFFE01204 // Instruction Cache 1 Status
#define ICPLB_DATA2 0xFFE01208 // Instruction Cache 2 Status
#define ICPLB_DATA3 0xFFE0120C // Instruction Cache 3 Status
#define ICPLB_DATA4 0xFFE01210 // Instruction Cache 4 Status
#define ICPLB_DATA5 0xFFE01214 // Instruction Cache 5 Status
#define ICPLB_DATA6 0xFFE01218 // Instruction Cache 6 Status
#define ICPLB_DATA7 0xFFE0121C // Instruction Cache 7 Status
#define ICPLB_DATA8 0xFFE01220 // Instruction Cache 8 Status
#define ICPLB_DATA9 0xFFE01224 // Instruction Cache 9 Status
#define ICPLB_DATA10 0xFFE01228 // Instruction Cache 10 Status
#define ICPLB_DATA11 0xFFE0122C // Instruction Cache 11 Status
#define ICPLB_DATA12 0xFFE01230 // Instruction Cache 12 Status
#define ICPLB_DATA13 0xFFE01234 // Instruction Cache 13 Status
#define ICPLB_DATA14 0xFFE01238 // Instruction Cache 14 Status
#define ICPLB_DATA15 0xFFE0123C // Instruction Cache 15 Status
#define ITEST_COMMAND 0xFFE01300 // Instruction Test Command Register
#define ITEST_INDEX 0xFFE01304 // Instruction Test Index Register
#define ITEST_DATA0 0xFFE01400 // Instruction Test Data Register
#define ITEST_DATA1 0xFFE01404 // Instruction Test Data Register
// Event/Interrupt Registers
#define EVT0 0xFFE02000 // Event Vector 0 ESR Address
#define EVT1 0xFFE02004 // Event Vector 1 ESR Address
#define EVT2 0xFFE02008 // Event Vector 2 ESR Address
#define EVT3 0xFFE0200C // Event Vector 3 ESR Address
#define EVT4 0xFFE02010 // Event Vector 4 ESR Address
#define EVT5 0xFFE02014 // Event Vector 5 ESR Address
#define EVT6 0xFFE02018 // Event Vector 6 ESR Address
#define EVT7 0xFFE0201C // Event Vector 7 ESR Address
#define EVT8 0xFFE02020 // Event Vector 8 ESR Address
#define EVT9 0xFFE02024 // Event Vector 9 ESR Address
#define EVT10 0xFFE02028 // Event Vector 10 ESR Address
#define EVT11 0xFFE0202C // Event Vector 11 ESR Address
#define EVT12 0xFFE02030 // Event Vector 12 ESR Address
#define EVT13 0xFFE02034 // Event Vector 13 ESR Address
#define EVT14 0xFFE02038 // Event Vector 14 ESR Address
#define EVT15 0xFFE0203C // Event Vector 15 ESR Address
#define EVT_OVERRIDE 0xFFE02100 // Event Vector Table Override Register
#define IMASK 0xFFE02104 // Interrupt Mask Register
#define IPEND 0xFFE02108 // Interrupt Pending Register
#define ILAT 0xFFE0210C // Interrupt Latch Register
// Core Timer Registers
#define TCNTL 0xFFE03000 // Core Timer Control Register
#define TPERIOD 0xFFE03004 // Core Timer Period Register
#define TSCALE 0xFFE03008 // Core Timer Scale Register
#define TCOUNT 0xFFE0300C // Core Timer Count Register
// Debug/MP/Emulation Registers
#define DSPID 0xFFE05000 // DSP Processor ID Register for MP implementations
#define DBGCTL 0xFFE05004 // Debug Control Register
#define DBGSTAT 0xFFE05008 // Debug Status Register
#define EMUDAT 0xFFE0500C // Emulator Data Register
// Trace Buffer Registers
#define TBUFCTL 0xFFE06000 // Trace Buffer Control Register
#define TBUFSTAT 0xFFE06004 // Trace Buffer Status Register
#define TBUF 0xFFE06100 // Trace Buffer
// Watch Point Control Registers
#define WPIACTL 0xFFE07000 // Instruction Watch Point Control Register
#define WPIA0 0xFFE07040 // Instruction Watch Point Address 0
#define WPIA1 0xFFE07044 // Instruction Watch Point Address 1
#define WPIA2 0xFFE07048 // Instruction Watch Point Address 2
#define WPIA3 0xFFE0704C // Instruction Watch Point Address 3
#define WPIA4 0xFFE07050 // Instruction Watch Point Address 4
#define WPIA5 0xFFE07054 // Instruction Watch Point Address 5
#define WPIACNT0 0xFFE07080 // Instruction Watch Point Counter 0
#define WPIACNT1 0xFFE07084 // Instruction Watch Point Counter 1
#define WPIACNT2 0xFFE07088 // Instruction Watch Point Counter 2
#define WPIACNT3 0xFFE0708C // Instruction Watch Point Counter 3
#define WPIACNT4 0xFFE07090 // Instruction Watch Point Counter 4
#define WPIACNT5 0xFFE07094 // Instruction Watch Point Counter 5
#define WPDACTL 0xFFE07100 // Data Watch Point Control Register
#define WPDA0 0xFFE07140 // Data Watch Point Address 0
#define WPDA1 0xFFE07144 // Data Watch Point Address 1
#define WPDACNT0 0xFFE07180 // Data Watch Point Counter 0
#define WPDACNT1 0xFFE07184 // Data Watch Point Counter 1
#define WPSTAT 0xFFE07200 // Watch Point Status Register
// Performance Monitor Registers
#define PFCTL 0xFFE08000 // Performance Monitor Control Register
#define PFCNTR0 0xFFE08100 // Performance Monitor Counter Register 0
#define PFCNTR1 0xFFE08104 // Performance Monitor Counter Register 1
//**********************************************************************************
// Core MMR Register Bits
//**********************************************************************************
//**************************************************
// EVT registers (ILAT, IMASK, and IPEND).
//**************************************************
// ** Bit Positions
#define EVT_EMU_P 0x00000000 // Emulator interrupt bit position
#define EVT_RST_P 0x00000001 // Reset interrupt bit position
#define EVT_NMI_P 0x00000002 // Non Maskable interrupt bit position
#define EVT_EVX_P 0x00000003 // Exception bit position
#define EVT_IRPTEN_P 0x00000004 // Global interrupt enable bit position
#define EVT_IVHW_P 0x00000005 // Hardware Error interrupt bit position
#define EVT_IVTMR_P 0x00000006 // Timer interrupt bit position
#define EVT_IVG7_P 0x00000007 // IVG7 interrupt bit position
#define EVT_IVG8_P 0x00000008 // IVG8 interrupt bit position
#define EVT_IVG9_P 0x00000009 // IVG9 interrupt bit position
#define EVT_IVG10_P 0x0000000a // IVG10 interrupt bit position
#define EVT_IVG11_P 0x0000000b // IVG11 interrupt bit position
#define EVT_IVG12_P 0x0000000c // IVG12 interrupt bit position
#define EVT_IVG13_P 0x0000000d // IVG13 interrupt bit position
#define EVT_IVG14_P 0x0000000e // IVG14 interrupt bit position
#define EVT_IVG15_P 0x0000000f // IVG15 interrupt bit position
// ** Masks
#define EVT_EMU MK_BMSK_(EVT_EMU_P ) // Emulator interrupt mask
#define EVT_RST MK_BMSK_(EVT_RST_P ) // Reset interrupt mask
#define EVT_NMI MK_BMSK_(EVT_NMI_P ) // Non Maskable interrupt mask
#define EVT_EVX MK_BMSK_(EVT_EVX_P ) // Exception mask
#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) // Global interrupt enable mask
#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) // Hardware Error interrupt mask
#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) // Timer interrupt mask
#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) // IVG7 interrupt mask
#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) // IVG8 interrupt mask
#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) // IVG9 interrupt mask
#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) // IVG10 interrupt mask
#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) // IVG11 interrupt mask
#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) // IVG12 interrupt mask
#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) // IVG13 interrupt mask
#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) // IVG14 interrupt mask
#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) // IVG15 interrupt mask
//**************************************************
// DMEM_CONTROL register
//**************************************************
// ** Bit Positions
#define DMCTL_ENDM_P 0x00000000 // Enable Data Memory L1
#define DMCTL_DMC0_P 0x00000001 // Data Memory Configuration, 00 - A SRAM, B SRAM
#define DMCTL_DMC1_P 0x00000002 // Data Memory Configuration, 10 - A SRAM, B SRAM
#define DMCTL_DMC2_P 0x00000003 // Data Memory Configuration, 11 - A CACHE, B CACHE
// ** Masks
#define ENDM MK_BMSK_(DMCTL_ENDM_P) // Enable Data Memory L1
// Bank A set as SRAM, Bank B set as SRAM
#define ASRAM_BSRAM 0x00000000
// Enable DCPLB
#define ENDCPLB MK_BMSK_(DMCTL_DMC0_P) | \
0
// Bank A set as CACHE, Bank B set as SRAM
#define ACACHE_BSRAM 0x00000008
// Bank A set as CACHE, Bank B set as CACHE
#define ACACHE_BCACHE 0x0000000C
#define DCBS 0x00000010 // If HIGHBIT is 1, select L1 data memory B
// If HIGHBIT is 0, select L1 data memory A
// If LOWBIT is 1, select L1 memory bank B
// If LOWBIT is 0, select L1 memory bank A
// IMEM_CONTROL Masks
#define ENIM 0x00000001 // Enable L1 Code Memory
#define ENICPLB 0x00000002 // Enable ICPLB
#define IMC 0x00000004 // Configure L1 code memory as cache (0=SRAM)
// TCNTL Masks
#define TMPWR 0x00000001 // Timer Low Power Control, 0=low power mode, 1=active state
#define TMREN 0x00000002 // Timer enable, 0=disable, 1=enable
#define TAUTORLD 0x00000004 // Timer auto reload
#define TINT 0x00000008 // Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky)
// TCNTL Bit Positions
#define TMPWR_P 0x00000000 // Timer Low Power Control, 0=low power mode, 1=active state
#define TMREN_P 0x00000001 // Timer enable, 0=disable, 1=enable
#define TAUTORLD_P 0x00000002 // Timer auto reload
#define TINT_P 0x00000003 // Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky)
// DCPLB_DATA and ICPLB_DATA Masks
#define CPLB_VALID 0x00000001 // 0=invalid entry, 1=valid entry
#define CPLB_LOCK 0x00000002 // 0=entry may be replaced, 1=entry locked
#define CPLB_USER_RD 0x00000004 // 0=no read access, 1=read access allowed (user mode)
#define CPLB_USER_WR 0x00000008 // 0=no write access, 0=write access allowed (user mode)
// only applies to L1 data memory
#define CPLB_SUPV_WR 0x00000010 // 0=no write access, 0=write access allowed (supervisor mode)
#define CPLB_L1SRAM 0x00000020 // 0=SRAM mapped in L1, 0=SRAM not mapped to L1
#define CPLB_DA0ACC 0x00000040 // 0=access allowed from either DAG, 1=access from DAG0 only
// only applies in L1 data memory controller
#define CPLB_DIRTY 0x00000080 // 0=dirty, 1=clean
// only applies in L1 data memory controller
#define CPLB_L1_CHBL 0x00001000 // 0=non-cacheable in L1, 1=cacheable in L1
#define CPLB_L2_CHBL 0x00002000 // 0=non-cacheable in L2, 1=cacheable in L2
#define CPLB_WT 0x00004000 // 0=write-back, 1=write-through
// only applies in L1 data memory controller in cache mode
#define PAGE_SIZE_1KB 0x00000000 // 1 KB page size
#define PAGE_SIZE_4KB 0x00010000 // 4 KB page size
#define PAGE_SIZE_1MB 0x00020000 // 1 MB page size
#define PAGE_SIZE_4MB 0x00030000 // 4 MB page size
// DCPLB_DATA and ICPLB_DATA Bit Positions
#define CPLB_VALID_P 0x00000000 // 0=invalid entry, 1=valid entry
#define CPLB_LOCK_P 0x00000001 // 0=entry may be replaced, 1=entry locked
#define CPLB_USER_RD_P 0x00000002 //
#endif // #ifdef DEF_BLACKFIN_H
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