defblackfin.h

基于ADSP 的PCI 代码

/*
** Copyright (C) 2001 Analog Devices Inc., All Rights Rerserved.
*/
//**********************************************************************************
// defblackfin.h - SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-21535
// Last Revised: 5/16/01 JN, ADI
//
// This include file contains a list of macro "defines" to enable the programmer
// to use symbolic names for the following ADSP-21535 facilities:
//  
//  - System Register bit definitions
//  - Core MMR Register map
//  - System MMR Register map
//  - *some* Core MMR Register bit definitions
//  - *some* System MMR Register bit definitions
//
// Here is an example use for setting a bit in a system register using bitset and a bit position:
// The example enables the cycle counter in SYSCFG.
//
//  r0 = SYSCFG;
// bitset (r0, CCEN_BIT);
// SYSCFG = r0;
//
// Here is an example use for clearing a bit in a system register using bitclr and a bit position:
// The example disables the cycle counter in SYSCFG.
//
//  r0 = SYSCFG;
// bitclr (r0, CCEN_BIT);
// SYSCFG = r0;
//
//
// Here is an example use for setting multiple bits in a system register using a mask:
// The example enables the cycle counter and supervisor single step in SYSCFG.
//
//  r0 = SYSCFG;
// r1.l = (CCEN | SSSTEP) & 0xffff;
// r1.h = (CCEN | SSSTEP) >> 16;
// r0 = r0 | r1;
// SYSCFG = r0;
//
// Here is an example use for clearing multiple bits in a system register using a mask:
// The example disables the cycle counter and supervisor single step in SYSCFG.
//
//  r0 = SYSCFG;
// r0 =~ r0;
// r1.l = (CCEN | SSSTEP) & 0xffff;
// r1.h = (CCEN | SSSTEP) >> 16;
// r0 = r0 | r1;
//  r0 =~ r0;
// SYSCFG = r0;
//
//**********************************************************************************

#ifndef __DEF_BLACKFIN_H_
#define __DEF_BLACKFIN_H_

#define MK_BMSK_( x ) (1<<x)    // Make a bit mask from a bit position

//**********************************************************************************
// System Register Bits
//**********************************************************************************

//**************************************************
//   ASTAT register
//**************************************************

#ifdef __ADSP21535__
// ** Bit Positions
#define ASTAT_AZ_P         0x00000000                  // Result of last ALU0 or shifter operation is zero
#define ASTAT_AN_P         0x00000001                  // Result of last ALU0 or shifter operation is negative
#define ASTAT_AC_P         0x00000002                  // Result of last ALU0 operation generated a carry
#define ASTAT_AV0_P        0x00000003                  // Result of last ALU0 or MAC0 operation overflowed, sticky for MAC
#define ASTAT_AV1_P        0x00000004                  // Result of last MAC1 operation overflowed, sticky for MAC
#define ASTAT_CC_P         0x00000005                  // Condition Code, used for holding comparison results
#define ASTAT_AQ_P         0x00000006                  // Quotient Bit
#define ASTAT_RND_MOD_P    0x00000008                  // Rounding mode, set for biased, clear for unbiased

// NOTE: ASTAT_AC_P will be deprecated in future releases
// To be replaced by ASTAT_AC0_P
#define ASTAT_AC0_P        ASTAT_AC_P

#else	/* __ADSP21535__ */

// definitions of ASTAT bit positions for next revision of BLACKFIN
#define ASTAT_AZ_P         0x00000000                  // Result of last ALU0 or shifter operation is zero
#define ASTAT_AN_P         0x00000001                  // Result of last ALU0 or shifter operation is negative
#define ASTAT_CC_P         0x00000005                  // Condition Code, used for holding comparison results
#define ASTAT_AQ_P         0x00000006                  // Quotient Bit
#define ASTAT_RND_MOD_P    0x00000008                  // Rounding mode, set for biased, clear for unbiased
#define ASTAT_AC0_P        0x0000000C                  // Result of last ALU0 operation generated a carry
#define ASTAT_AC1_P        0x0000000D                  // Result of last ALU1 operation generated a carry
#define ASTAT_AV0_P        0x00000010                  // Result of last ALU0 or MAC0 operation overflowed, sticky for MAC
#define ASTAT_AV0S_P       0x00000011                  // Sticky version of ASTAT_AV0_P
#define ASTAT_AV1_P        0x00000012                  // Result of last MAC1 operation overflowed, sticky for MAC
#define ASTAT_AV1S_P       0x00000013                  // Sticky version of ASTAT_AV1_P
#define ASTAT_V_P          0x00000018                  // Result of last op written to data register file.
#define ASTAT_VS_P         0x00000019                  // Sticky version of ASTAT_V_P
#endif /* __ADSP21535__ */

// ** Masks
#define ASTAT_AZ           MK_BMSK_(ASTAT_AZ_P)        // Result of last ALU0 or shifter operation is zero
#define ASTAT_AN           MK_BMSK_(ASTAT_AN_P)        // Result of last ALU0 or shifter operation is negative
#define ASTAT_AV0          MK_BMSK_(ASTAT_AV0_P)       // Result of last ALU0 or MAC0 operation overflowed, sticky for MAC
#define ASTAT_AV1          MK_BMSK_(ASTAT_AV1_P)       // Result of last MAC1 operation overflowed, sticky for MAC
#define ASTAT_CC           MK_BMSK_(ASTAT_CC_P)        // Condition Code, used for holding comparison results
#define ASTAT_AQ           MK_BMSK_(ASTAT_AQ_P)        // Quotient Bit
#define ASTAT_RND_MOD      MK_BMSK_(ASTAT_RND_MOD_P)   // Rounding mode, set for biased, clear for unbiased

#ifdef __ADSP21535__

#define ASTAT_AC           MK_BMSK_(ASTAT_AC_P)        // Result of last ALU0 operation generated a carry

#else /* __ADSP21535__ */

#define ASTAT_AC0          MK_BMSK_(ASTAT_AC0_P)       // Result of last ALU0 operation generated a carry
#define ASTAT_AC1          MK_BMSK_(ASTAT_AC1_P)       // Result of last ALU1 operation generated a carry
#define ASTAT_AV0S         MK_BMSK_(ASTAT_AV0S_P)      // Sticky version of ASTAT_AV0_P
#define ASTAT_AV1S         MK_BMSK_(ASTAT_AV1S_P)      // Sticky version of ASTAT_AV1_P
#define ASTAT_V            MK_BMSK_(ASTAT_V_P)         // Result of last op written to data register file.
#define ASTAT_VS           MK_BMSK_(ASTAT_VS_P)        // Sticky version of ASTAT_V_P

#endif	/* __ADSP21535__ */

//**************************************************
//   SEQSTAT register
//**************************************************

// ** Bit Positions
#define SEQSTAT_EXCAUSE0_P     0x00000000     // Last exception cause bit 0
#define SEQSTAT_EXCAUSE1_P     0x00000001  // Last exception cause bit 1
#define SEQSTAT_EXCAUSE2_P     0x00000002  // Last exception cause bit 2
#define SEQSTAT_EXCAUSE3_P     0x00000003  // Last exception cause bit 3
#define SEQSTAT_EXCAUSE4_P     0x00000004  // Last exception cause bit 4
#define SEQSTAT_EXCAUSE5_P     0x00000005  // Last exception cause bit 5
#define SEQSTAT_OMODE0_P       0x0000000A  // Operating mode: 00 user, 01 supervisor, 1x debug
#define SEQSTAT_OMODE1_P       0x0000000B  // Operating mode: 00 user, 01 supervisor, 1x debug
#define SEQSTAT_IDLE_REQ_P     0x0000000C  // Pending idle mode request, set by IDLE instruction
#define SEQSTAT_SFTRESET_P     0x0000000D  // Indicates whether the last reset was a software reset (=1)
#define SEQSTAT_HWERRCAUSE0_P  0x0000000E  // Last hw error cause bit 0
#define SEQSTAT_HWERRCAUSE1_P  0x0000000F  // Last hw error cause bit 1
#define SEQSTAT_HWERRCAUSE2_P  0x00000010  // Last hw error cause bit 2
#define SEQSTAT_HWERRCAUSE3_P  0x00000011  // Last hw error cause bit 3
#define SEQSTAT_HWERRCAUSE4_P  0x00000012  // Last hw error cause bit 4

// ** Masks
// Exception cause
#define SEQSTAT_EXCAUSE        MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
                               MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
                               MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
                               MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
                               MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
                               MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
                               0

// Operating mode: 00 user, 01 supervisor, 1x debug
#define SEQSTAT_OMODE          MK_BMSK_(SEQSTAT_OMODE0_P) | \
                               MK_BMSK_(SEQSTAT_OMODE1_P) | \
                               0

// Pending idle mode request, set by IDLE instruction
#define SEQSTAT_IDLE_REQ       MK_BMSK_(SEQSTAT_IDLE_REQ_P)

// Indicates whether the last reset was a software reset (=1)
#define SEQSTAT_SFTRESET       MK_BMSK_(SEQSTAT_SFTRESET_P)

// Last hw error cause
#define SEQSTAT_HWERRCAUSE     MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
                               MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
                               MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
                               MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
                               MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
                               0

//**************************************************
//   SYSCFG register
//**************************************************

// ** Bit Positions
#define SYSCFG_SSSTEP_P        0x00000000              // Supervisor single step, when set it forces an exception for each instruction executed
#define SYSCFG_CCEN_P          0x00000001              // Enable cycle counter (=1)

// ** Masks
#define SYSCFG_SSSSTEP         MK_BMSK_(SYSCFG_SSSTEP_P)   // Supervisor single step, when set it forces an exception for each instruction executed
#define SYSCFG_CCCEN           MK_BMSK_(SYSCFG_CCEN_P)     // Enable cycle counter (=1)


//**********************************************************************************
// Core MMR Register Map
//**********************************************************************************

// Cache & SRAM Memory
#define SRAM_BASE_ADDRESS      0xFFE00000  // SRAM Base Address (Read Only)
#define DMEM_CONTROL           0xFFE00004  // Data memory control
#define DCPLB_STATUS           0xFFE00008  // Data Cache Programmable Look-Aside Buffer Status
#define DCPLB_FAULT_ADDR       0xFFE0000C  // Data Cache Programmable Look-Aside Buffer Fault Address
#define MMR_TIMEOUT            0xFFE00010  // Memory-Mapped Register Timeout Register
#define DCPLB_ADDR0            0xFFE00100  // Data Cache Protection Lookaside Buffer 0
#define DCPLB_ADDR1            0xFFE00104  // Data Cache Protection Lookaside Buffer 1
#define DCPLB_ADDR2            0xFFE00108  // Data Cache Protection Lookaside Buffer 2
#define DCPLB_ADDR3            0xFFE0010C  // Data Cache Protection Lookaside Buffer 3
#define DCPLB_ADDR4            0xFFE00110  // Data Cache Protection Lookaside Buffer 4
#define DCPLB_ADDR5            0xFFE00114  // Data Cache Protection Lookaside Buffer 5
#define DCPLB_ADDR6            0xFFE00118  // Data Cache Protection Lookaside Buffer 6
#define DCPLB_ADDR7            0xFFE0011C  // Data Cache Protection Lookaside Buffer 7
#define DCPLB_ADDR8            0xFFE00120  // Data Cache Protection Lookaside Buffer 8
#define DCPLB_ADDR9            0xFFE00124  // Data Cache Protection Lookaside Buffer 9
#define DCPLB_ADDR10           0xFFE00128  // Data Cache Protection Lookaside Buffer 10
#define DCPLB_ADDR11           0xFFE0012C  // Data Cache Protection Lookaside Buffer 11
#define DCPLB_ADDR12           0xFFE00130  // Data Cache Protection Lookaside Buffer 12
#define DCPLB_ADDR13           0xFFE00134  // Data Cache Protection Lookaside Buffer 13
#define DCPLB_ADDR14           0xFFE00138  // Data Cache Protection Lookaside Buffer 14
#define DCPLB_ADDR15           0xFFE0013C  // Data Cache Protection Lookaside Buffer 15
#define DCPLB_DATA0            0xFFE00200  // Data Cache 0 Status
#define DCPLB_DATA1            0xFFE00204  // Data Cache 1 Status
#define DCPLB_DATA2            0xFFE00208  // Data Cache 2 Status
#define DCPLB_DATA3            0xFFE0020C  // Data Cache 3 Status
#define DCPLB_DATA4            0xFFE00210  // Data Cache 4 Status
#define DCPLB_DATA5            0xFFE00214  // Data Cache 5 Status
#define DCPLB_DATA6            0xFFE00218  // Data Cache 6 Status
#define DCPLB_DATA7            0xFFE0021C  // Data Cache 7 Status
#define DCPLB_DATA8            0xFFE00220  // Data Cache 8 Status
#define DCPLB_DATA9            0xFFE00224  // Data Cache 9 Status
#define DCPLB_DATA10           0xFFE00228  // Data Cache 10 Status
#define DCPLB_DATA11           0xFFE0022C  // Data Cache 11 Status
#define DCPLB_DATA12           0xFFE00230  // Data Cache 12 Status
#define DCPLB_DATA13           0xFFE00234  // Data Cache 13 Status
#define DCPLB_DATA14           0xFFE00238  // Data Cache 14 Status
#define DCPLB_DATA15           0xFFE0023C  // Data Cache 15 Status
#define DTEST_COMMAND          0xFFE00300  // Data Test Command Register
#define DTEST_INDEX            0xFFE00304  // Data Test Index Register
#define DTEST_DATA0            0xFFE00400  // Data Test Data Register