blinkdevhost.asm_bak

基于ADSP 的PCI 代码

#include "defBF535.h"
#include "pci_ids.h"
#include "My_Header.h"

#define ASYNCB0		0x20000000

.section L2_data;
.align 4;
.var buff[1024];
.var back_buff[1024];


.SECTION program2;

.GLOBAL DMA_TO_TARGET;


.align 4;
DMA_TO_TARGET:

[--SP] = RETS; // push return address

/********* write to MBAP with the address of the host's intended destination  ****************/
P4.H = (PCI_MBAP >> 16); P4.L = (PCI_MBAP & 0xFFFF);
R0.H = L2_BASE >> 16;  R0.L = L2_BASE & 0xFFFF;  
[P4] = R0;
ssync;



	
	p5 = 0x400;
	p4.h = buff; p4.l = buff;
	r0.l = 0x0; r0.h = 0x1234;
	r1 = 0x1111;   r1.h = 0x5678;
	LSETUP(lstart, lfinish) LC0 = P5;
	lstart: r0 = r0 + r1;
	r3 = r0 + r1;
	lfinish:  [p4++] = r3; 


R0.L = START;
R1.L = END;
R0 = R1 - R0;

//r0 = 0x1000;  1k words (each word = 4 bytes)
P0.L = READ;
P0.H = READ;
P1.L = WRITE;
P1.H = WRITE;
P2.L = MDR_DND & 0xFFFF;
P2.H = (MDR_DND >> 16) & 0xFFFF;	//sDMA Memory DMA Next Descriptor Pointer Register
P3.L = DB_NDBP & 0xFFFF;
P3.H = (DB_NDBP >> 16) & 0xFFFF;	//DMA Next Descriptor Base Pointer Register
P4.L = MDW_DND & 0xFFFF;			
P4.H = (MDW_DND >> 16) & 0xFFFF;	//pDMA Memory DMA Next Descriptor Pointer Register
P5.L = MDR_DCFG & 0xFFFF;
P5.H = (MDR_DCFG >> 16) & 0xFFFF;	//sDMA Memory Config Register
I0.L = MDW_DCFG & 0xFFFF;
I0.H = (MDW_DCFG >> 16) & 0xFFFF;	//pDMA Memory Config Register
I1.L = MDR_DSAH & 0xFFFF;
I1.H = (MDR_DSAH >> 16) & 0xFFFF;	//sDMA Memory Start Address High Register
I2.L = MDR_DSAL & 0xFFFF;
I2.H = (MDR_DSAL >> 16) & 0xFFFF;	//sDMA Memory Start Address Low Register

/***********************DMA to L1 Code***********************************************************/
//R0.H = 0x9009;						//sDMA Config Word (8-bit transfers)
//R0.H = 0x8001;						//sDMA Config Word (16-bit transfers)
R0.H = 0x8009;						//sDMA Config Word (32-bit transfers)
 R1.L = START;						//sDMA Start Address Low
 R1.H = START;						//sDMA Start Address High
// r1.l = buff; r1.h = buff;

R2.L = END_DMA;						//sDMA Next Descriptor Pointer

//R2.H = 0x900B;						//pDMA Config Word (8-bit transfers)
//R2.H = 0x8003;						//pDMA Config Word (16-bit transfers)
R2.H = 0x800B;						//pDMA Config Word (32-bit transfers)
R3.L = Memory_Window & 0xFFFF;			//pDMA Start Address Low = PCI MEM WINDOW
R3.H = Memory_Window >> 16;				//pDMA Start Address High = PCI MEM WINDOW
R4.L = END_DMA;




CALL Setup_TCB;
CALL Enable_DMA;
/************************************************************************************************/


DMA_TO_TARGET.END: RETS = [SP++]; // Pop return address
RTS;  

IDLE;
SSYNC;

/********TCB Setup**********/
Setup_TCB:

W[P0+0x2] = R0;						//sDMA Count
[P0+0x4] = R1;						//sDMA Start Address
W[P0+0x8] = R2; 					//sDMA Next Descriptor Pointer

W[P1+0x2] = R0;						//pDMA Count
[P1+0x4] = R3;						//pDMA Start Address
W[P1+0x8] = R4;						//pDMA Next Descriptor Pointer

W[P0] = R0.H;						//sDMA Config Word
W[P1] = R2.H;						//pDMA Config Word
RTS;
/***************************/

/********Enable DMA*********/
Enable_DMA:
R6 = P0;
W[P2] = R6.L;						//sDMA Memory DMA Next Descriptor Pointer Register = FLASH_READ
W[P3] = R6.H;						//DMA Next Descriptor Base Pointer Register

R6 = P1;
W[P4] = R6.L;						//pDMA Memory DMA Next Descriptor Pointer Register = FLASH_WRITE

R6 = W[P5];
BITSET(R6,0);						//Enable DMA for sDMA

R7.L = W[I0];
BITSET(R7,0);						//Enable DMA for pDMA

W[P5] = R6;
.ALIGN 4;
W[I0] = R7.L;
.ALIGN 4;
DMA_WAIT:							//Wait for DMA to Complete
R6 = W[P1];
cc = bittst(R6,15);
IF cc JUMP DMA_WAIT;

RTS;
/***************************/

/*******************************Application Code to be DMAed**********************/
START:
 	
	
	P0.L = FIO_DIR & 0xFFFF;
	P0.H = FIO_DIR >> 16;

	R0 = W[P0];
	R1.L = 0xF800;
	R0 = R0 | R1;
	W[P0] = R0;					//Set PF 15 - PF 11 as Outputs

	P1.L = FIO_FLAG_S & 0xFFFF;
	P1.H = FIO_FLAG_S >> 16;
	P2.L = FIO_FLAG_C & 0xFFFF;
	P2.H = FIO_FLAG_C >> 16;

	P5.H = 0x0353;
	P5.L=0x4600;			//Count to Generate Interrupt Every 2sec for 300MHz
	
	R1.L = 0xA800;			//Affect PF15, PF13, and PF11
	R2.L = 0x5000;			//Affect PF14 and PF 12

	LIGHT:
	W[P1] = R1;			//Set PF15, PF13, and PF11
	CSYNC;
	W[P2] = R2;			//Clear PF14 and PF12
	CSYNC;

	CALL DELAY_LOOP;
 
	W[P1] = R2;			//Set PF14 and PF12
	CSYNC;
	W[P2] = R1;			//Clear PF15, PF13, and PF11
	CSYNC;

	CALL DELAY_LOOP;

	JUMP LIGHT;

	DELAY_LOOP:        
	LSETUP(L_BEGIN, L_END) LC0 = P5;
	L_BEGIN:
	L_END: NOP;    
	RTS;         
END:	NOP; 
/************************************************************************************/

.align 4;
.BYTE2 READ[5];
.align 4;
.BYTE2 WRITE[5];
.align 4;
.BYTE2 END_DMA[1] = 0x0;