constraints.tcl

hdlc_receive_code.rar

#Create user 
set CLK_PORT [get_ports ihdlc_RXCLK]
#set CLK_PORT1 [get_ports pad_iOsc]
set CLK_PERIOD 50 
set DRIVE_CELL POL8W
set LOAD SP018W_V1p4_max/PISDW/PAD
set MAX_BLOCK 5
set MAX_CAPACITANCE 1
set MAX_FANOUT 15
set MAX_TRANSITION 1
set INPUT_DELAY 5
set OUTPUT_DELAY 5
set ALL_INS_EX_CLK [remove_from_collection [all_inputs] [get_ports ihdlc_RXCLK]]
#set ALL_INS_EX_CLK [remove_from_collection $ALL_INS_EX_CLK0 [get_ports pad_iOsc]]

#Reset the design
reset_design

#Operating Environment
set_operating_conditions slow
set_wire_load_model -name ForQA
set_wire_load_mode enclosed
set_driving_cell -lib_cell $DRIVE_CELL $ALL_INS_EX_CLK
set_load -pin_load [expr [load_of $LOAD] * $MAX_BLOCK] [all_outputs]

#Design Rule Constraints
set_max_capacitance $MAX_CAPACITANCE $ALL_INS_EX_CLK
set_max_fanout $MAX_FANOUT $ALL_INS_EX_CLK
set_max_transition $MAX_TRANSITION $ALL_INS_EX_CLK

#et_dont_touch [get_cells {input* output*}]

#Optimization Constraints
set_max_area 0

#Create clock and Define Timing Constraints
set_clock_latency  1  [get_ports ihdlc_RXCLK]
set_clock_uncertainty  -setup 3  [get_ports ihdlc_RXCLK]
set_clock_uncertainty -hold 3  [get_ports ihdlc_RXCLK]
create_clock -name  ihdlc_RXCLK -period $CLK_PERIOD -waveform {0 30} $CLK_PORT
set_dont_touch_network $CLK_PORT
#create_clock -name pad_iOsc -period $CLK_PERIOD -waveform {0 25} $CLK_PORT1
#set_dont_touch_network $CLK_PORT1

set_input_delay -max $INPUT_DELAY -clock ihdlc_RXCLK $ALL_INS_EX_CLK
#set_input_delay -max $INPUT_DELAY -clock pad_iOsc $ALL_INS_EX_CLK
set_output_delay -max $OUTPUT_DELAY -clock ihdlc_RXCLK [all_outputs]
#set_output_delay -max $OUTPUT_DELAY -clock pad_iOsc [all_outputs]

#set_false_path -to [get_ports pad_oClk]