analyze.tcl

hdlc_receive_code.rar

#analyze -f verilog ~/ip/SincFilter.v
#analyze -f verilog ../source/tape_out/Buffer.v 
#analyze -f verilog ../source/tape_out/ChipTop.v
#analyze -f verilog ../source/tape_out/DLY1X1.v
#analyze -f verilog ../source/tape_out/DW_fifoctl_s2_sf.v
#analyze -f verilog ../source/tape_out/DW_fifo_s2_sf.v
#analyze -f verilog ../source/tape_out/DW_ram_r_w_s_dff.v
#analyze -f verilog ../source/tape_out/FIFO.v
#analyze -f verilog ../source/tape_out/I2C.v
#analyze -f verilog ../source/tape_out/ModuleTop.v
#analyze -f verilog ../source/tape_out/RanInit.v
#analyze -f verilog ../source/tape_out/Shuffle.v
#analyze -f verilog ../source/tape_out/MUX.v
#analyze -f verilog ../source/tape_out/RstSync.v
#analyze -f verilog ../source/tape_out/Rng2Way.v
#analyze -f verilog ../source/tape_out/RstGen.v
#analyze -f verilog ../source/tape_out/Start.v
#analyze -f verilog ../source/tape_out/Stop.v
analyze -f verilog  ../hdlc_recv.v