hdlc_recv.sdc

hdlc_receive_code.rar

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# Created by write_script -format dctcl on Fri Apr 18 14:00:36 2008

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# Set the current_design #
current_design hdlc_recv

set_operating_conditions slow -library slow
set_wire_load_mode enclosed
set_wire_load_model -name ForQA -library slow
set_max_area 0
set_driving_cell -lib_cell POL8W [get_ports ihdlc_RXD]
set_driving_cell -lib_cell POL8W [get_ports ihdlc_RESET]
set_dont_touch_network [get_ports ihdlc_RXCLK]
set_load -pin_load 33.55 [get_ports {ohdlc_TXD[7]}]
set_load -pin_load 33.55 [get_ports {ohdlc_TXD[6]}]
set_load -pin_load 33.55 [get_ports {ohdlc_TXD[5]}]
set_load -pin_load 33.55 [get_ports {ohdlc_TXD[4]}]
set_load -pin_load 33.55 [get_ports {ohdlc_TXD[3]}]
set_load -pin_load 33.55 [get_ports {ohdlc_TXD[2]}]
set_load -pin_load 33.55 [get_ports {ohdlc_TXD[1]}]
set_load -pin_load 33.55 [get_ports {ohdlc_TXD[0]}]
set_load -pin_load 33.55 [get_ports ohdlc_TXCLK]
set_load -pin_load 33.55 [get_ports {ohdlc_TXDS[2]}]
set_load -pin_load 33.55 [get_ports {ohdlc_TXDS[1]}]
set_load -pin_load 33.55 [get_ports {ohdlc_TXDS[0]}]
set_max_capacitance 1 [get_ports ihdlc_RXD]
set_max_capacitance 1 [get_ports ihdlc_RESET]
set_max_fanout 15 [get_ports ihdlc_RXD]
set_max_fanout 15 [get_ports ihdlc_RESET]
set_max_transition 1 [get_ports ihdlc_RXD]
set_max_transition 1 [get_ports ihdlc_RESET]
create_clock [get_ports ihdlc_RXCLK]  -period 50  -waveform {0 30}
set_input_delay -clock ihdlc_RXCLK  -max 5  [get_ports ihdlc_RXD]
set_input_delay -clock ihdlc_RXCLK  -max 5  [get_ports ihdlc_RESET]
set_output_delay -clock ihdlc_RXCLK  -max 5  [get_ports {ohdlc_TXD[7]}]
set_output_delay -clock ihdlc_RXCLK  -max 5  [get_ports {ohdlc_TXD[6]}]
set_output_delay -clock ihdlc_RXCLK  -max 5  [get_ports {ohdlc_TXD[5]}]
set_output_delay -clock ihdlc_RXCLK  -max 5  [get_ports {ohdlc_TXD[4]}]
set_output_delay -clock ihdlc_RXCLK  -max 5  [get_ports {ohdlc_TXD[3]}]
set_output_delay -clock ihdlc_RXCLK  -max 5  [get_ports {ohdlc_TXD[2]}]
set_output_delay -clock ihdlc_RXCLK  -max 5  [get_ports {ohdlc_TXD[1]}]
set_output_delay -clock ihdlc_RXCLK  -max 5  [get_ports {ohdlc_TXD[0]}]
set_output_delay -clock ihdlc_RXCLK  -max 5  [get_ports ohdlc_TXCLK]
set_output_delay -clock ihdlc_RXCLK  -max 5  [get_ports {ohdlc_TXDS[2]}]
set_output_delay -clock ihdlc_RXCLK  -max 5  [get_ports {ohdlc_TXDS[1]}]
set_output_delay -clock ihdlc_RXCLK  -max 5  [get_ports {ohdlc_TXDS[0]}]
set_clock_latency 1  [get_ports ihdlc_RXCLK]
set_clock_uncertainty 3  [get_ports ihdlc_RXCLK]