report_design.rpt

hdlc_receive_code.rar

 
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Report : design
Design : hdlc_recv
Version: Y-2006.06
Date   : Fri Apr 18 14:03:17 2008
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Design allows ideal nets on clock nets.

Library(s) Used:

    slow (File: /jeepHome/library/smic18/fb/aci/sc-x/synopsys/slow.db)

Local Link Library:

    {slow.db, SP018W_V1p4_max.db}

Flip-Flop Types:

    No flip-flop types specified.

Latch Types:

    No latch types specified.

Operating Conditions:


    Operating Condition Name : slow
    Library : slow
    Process :   1.00
    Temperature : 125.00
    Voltage :   1.62
    Interconnect Model : balanced_tree

Wire Loading Model:

    Selected manually by the user.

Name           :   ForQA
Location       :   slow
Resistance     :   0
Capacitance    :   1
Area           :   1
Slope          :   1
Fanout   Length   Points Average Cap Std Deviation
--------------------------------------------------------------
     1     0.00
    10     0.00



Wire Loading Model Mode: enclosed.

Timing Ranges:

    No timing ranges specified.

Pin Input Delays:

    None specified.

Pin Output Delays:

    None specified.

Disabled Timing Arcs:

    No arcs disabled.

Required Licenses:

    ( *SynLib-Eval or DesignWare-Foundation )

    NOTE: licenses preceded by an asterix ('*') will only provide
         limited access to the design.

Design Parameters:

    None specified.
1