min_timing.rpt

hdlc_receive_code.rar

 
****************************************
Report : timing
        -path full_clock
        -delay min
        -nets
        -max_paths 1
        -transition_time
        -capacitance
Design : hdlc_recv
Version: Y-2006.06
Date   : Fri Apr 18 14:03:17 2008
****************************************

Operating Conditions: slow   Library: slow
Wire Load Model Mode: enclosed

  Startpoint: byte_rst_counter_reg[1]
              (rising edge-triggered flip-flop clocked by ihdlc_RXCLK)
  Endpoint: byte_rst_counter_reg[2]
            (rising edge-triggered flip-flop clocked by ihdlc_RXCLK)
  Path Group: ihdlc_RXCLK
  Path Type: min

  Des/Clust/Port     Wire Load Model       Library
  ------------------------------------------------
  hdlc_recv          ForQA                 slow

  Point                                       Fanout       Cap     Trans      Incr       Path
  ----------------------------------------------------------------------------------------------
  clock ihdlc_RXCLK (rise edge)                                               0.00       0.00
  clock network delay (ideal)                                                 1.00       1.00
  byte_rst_counter_reg[1]/CK (DFFRHQX1)                             0.00      0.00       1.00 r
  byte_rst_counter_reg[1]/Q (DFFRHQX1)                              0.12      0.30       1.30 f
  byte_rst_counter[1] (net)                     2         0.01                0.00       1.30 f
  U327/Y (DLY4X1)                                                   0.13      0.97       2.27 f
  n557 (net)                                    1         0.00                0.00       2.27 f
  U326/Y (DLY4X1)                                                   0.19      1.03       3.30 f
  n556 (net)                                    2         0.01                0.00       3.30 f
  U541/Y (AOI32X1)                                                  0.18      0.20       3.50 r
  n528 (net)                                    1         0.00                0.00       3.50 r
  U286/Y (AOI2BB2XL)                                                0.55      0.43       3.93 r
  n539 (net)                                    1         0.03                0.00       3.93 r
  U285/Y (INVX8)                                                    0.08      0.04       3.97 f
  N58 (net)                                     1         0.00                0.00       3.97 f
  byte_rst_counter_reg[2]/D (DFFRHQX1)                              0.08      0.00       3.97 f
  data arrival time                                                                      3.97

  clock ihdlc_RXCLK (rise edge)                                               0.00       0.00
  clock network delay (ideal)                                                 1.00       1.00
  clock uncertainty                                                           3.00       4.00
  byte_rst_counter_reg[2]/CK (DFFRHQX1)                                       0.00       4.00 r
  library hold time                                                          -0.03       3.97
  data required time                                                                     3.97
  ----------------------------------------------------------------------------------------------
  data required time                                                                     3.97
  data arrival time                                                                     -3.97
  ----------------------------------------------------------------------------------------------
  slack (MET)                                                                            0.00


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