📄 post_dft.spf
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STIL 1.0 { Design P2001.01;}Header { Title "Minimal STIL for design `hdlc_recv'"; Date "Fri Apr 18 14:01:51 2008"; Source "DFT Compiler Y-2006.06";}Signals { "ihdlc_RESET" In; "ihdlc_RXCLK" In; "ihdlc_RXD" In; "ohdlc_TXCLK" Out; "ohdlc_TXDS[0]" Out; "ohdlc_TXDS[1]" Out; "ohdlc_TXDS[2]" Out; "ohdlc_TXD[0]" Out; "ohdlc_TXD[1]" Out; "ohdlc_TXD[2]" Out; "ohdlc_TXD[3]" Out; "ohdlc_TXD[4]" Out; "ohdlc_TXD[5]" Out; "ohdlc_TXD[6]" Out; "ohdlc_TXD[7]" Out;}SignalGroups { "all_inputs" = '"ihdlc_RESET" + "ihdlc_RXCLK" + "ihdlc_RXD"'; "all_outputs" = '"ohdlc_TXCLK" + "ohdlc_TXDS[0]" + "ohdlc_TXDS[1]" + "ohdlc_TXDS[2]" + "ohdlc_TXD[0]" + "ohdlc_TXD[1]" + "ohdlc_TXD[2]" + "ohdlc_TXD[3]" + "ohdlc_TXD[4]" + "ohdlc_TXD[5]" + "ohdlc_TXD[6]" + "ohdlc_TXD[7]"'; "all_ports" = '"all_inputs" + "all_outputs"'; "_pi" = '"all_inputs"'; "_po" = '"all_outputs"';}ScanStructures {}Timing { WaveformTable "_default_WFT_" { Period '100ns'; Waveforms { "all_inputs" { 0 { '5ns' D; } } "all_inputs" { 1 { '5ns' U; } } "all_inputs" { Z { '5ns' Z; } } "all_inputs" { N { '5ns' N; } } "all_outputs" { X { '0ns' X; '95ns' X; } } "all_outputs" { H { '0ns' X; '95ns' H; } } "all_outputs" { T { '0ns' X; '95ns' T; } } "all_outputs" { L { '0ns' X; '95ns' L; } } } }}Procedures { "capture" { W "_default_WFT_"; V { "_pi" = ###; } V { "_po" = \r12 #; } }}MacroDefs { "test_setup" { W "_default_WFT_"; V { } V { } }}
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