📄 max_timing.rpt
字号:
****************************************Report : timing -path full_clock -delay max -nworst 5 -nets -max_paths 5 -transition_time -capacitanceDesign : hdlc_recvVersion: Y-2006.06Date : Fri Apr 18 14:03:17 2008****************************************Operating Conditions: slow Library: slowWire Load Model Mode: enclosed Startpoint: ohdlc_TXCLK_reg (rising edge-triggered flip-flop clocked by ihdlc_RXCLK) Endpoint: ohdlc_TXCLK (output port clocked by ihdlc_RXCLK) Path Group: ihdlc_RXCLK Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ hdlc_recv ForQA slow Point Fanout Cap Trans Incr Path ------------------------------------------------------------------------------- clock ihdlc_RXCLK (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ohdlc_TXCLK_reg/CK (DFFSXL) 0.00 0.00 1.00 r ohdlc_TXCLK_reg/Q (DFFSXL) 0.70 0.97 1.97 r n694 (net) 2 0.04 0.00 1.97 r U569/Y (CLKBUFX20) 11.61 6.64 8.60 r ohdlc_TXCLK (net) 1 33.55 0.00 8.60 r ohdlc_TXCLK (out) 11.61 0.00 8.60 r data arrival time 8.60 clock ihdlc_RXCLK (rise edge) 50.00 50.00 clock network delay (ideal) 0.00 50.00 output external delay -5.00 45.00 data required time 45.00 ------------------------------------------------------------------------------- data required time 45.00 data arrival time -8.60 ------------------------------------------------------------------------------- slack (MET) 36.40 Startpoint: ohdlc_TXCLK_reg (rising edge-triggered flip-flop clocked by ihdlc_RXCLK) Endpoint: ohdlc_TXCLK (output port clocked by ihdlc_RXCLK) Path Group: ihdlc_RXCLK Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ hdlc_recv ForQA slow Point Fanout Cap Trans Incr Path ------------------------------------------------------------------------------- clock ihdlc_RXCLK (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ohdlc_TXCLK_reg/CK (DFFSXL) 0.00 0.00 1.00 r ohdlc_TXCLK_reg/Q (DFFSXL) 0.41 0.72 1.72 f n694 (net) 2 0.04 0.00 1.72 f U569/Y (CLKBUFX20) 11.47 6.88 8.60 f ohdlc_TXCLK (net) 1 33.55 0.00 8.60 f ohdlc_TXCLK (out) 11.47 0.00 8.60 f data arrival time 8.60 clock ihdlc_RXCLK (rise edge) 50.00 50.00 clock network delay (ideal) 0.00 50.00 output external delay -5.00 45.00 data required time 45.00 ------------------------------------------------------------------------------- data required time 45.00 data arrival time -8.60 ------------------------------------------------------------------------------- slack (MET) 36.40 Startpoint: ohdlc_TXD_reg[0] (rising edge-triggered flip-flop clocked by ihdlc_RXCLK) Endpoint: ohdlc_TXD[0] (output port clocked by ihdlc_RXCLK) Path Group: ihdlc_RXCLK Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ hdlc_recv ForQA slow Point Fanout Cap Trans Incr Path ------------------------------------------------------------------------------- clock ihdlc_RXCLK (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ohdlc_TXD_reg[0]/CK (DFFRHQXL) 0.00 0.00 1.00 r ohdlc_TXD_reg[0]/Q (DFFRHQXL) 0.97 0.91 1.91 r n693 (net) 2 0.04 0.00 1.91 r U571/Y (CLKBUFX20) 11.61 6.66 8.58 r ohdlc_TXD[0] (net) 1 33.55 0.00 8.58 r ohdlc_TXD[0] (out) 11.61 0.00 8.58 r data arrival time 8.58 clock ihdlc_RXCLK (rise edge) 50.00 50.00 clock network delay (ideal) 0.00 50.00 output external delay -5.00 45.00 data required time 45.00 ------------------------------------------------------------------------------- data required time 45.00 data arrival time -8.58 ------------------------------------------------------------------------------- slack (MET) 36.42 Startpoint: ohdlc_TXD_reg[1] (rising edge-triggered flip-flop clocked by ihdlc_RXCLK) Endpoint: ohdlc_TXD[1] (output port clocked by ihdlc_RXCLK) Path Group: ihdlc_RXCLK Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ hdlc_recv ForQA slow Point Fanout Cap Trans Incr Path ------------------------------------------------------------------------------- clock ihdlc_RXCLK (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ohdlc_TXD_reg[1]/CK (DFFRHQXL) 0.00 0.00 1.00 r ohdlc_TXD_reg[1]/Q (DFFRHQXL) 0.97 0.91 1.91 r n692 (net) 2 0.04 0.00 1.91 r U572/Y (CLKBUFX20) 11.61 6.66 8.58 r ohdlc_TXD[1] (net) 1 33.55 0.00 8.58 r ohdlc_TXD[1] (out) 11.61 0.00 8.58 r data arrival time 8.58 clock ihdlc_RXCLK (rise edge) 50.00 50.00 clock network delay (ideal) 0.00 50.00 output external delay -5.00 45.00 data required time 45.00 ------------------------------------------------------------------------------- data required time 45.00 data arrival time -8.58 ------------------------------------------------------------------------------- slack (MET) 36.42 Startpoint: ohdlc_TXD_reg[2] (rising edge-triggered flip-flop clocked by ihdlc_RXCLK) Endpoint: ohdlc_TXD[2] (output port clocked by ihdlc_RXCLK) Path Group: ihdlc_RXCLK Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ hdlc_recv ForQA slow Point Fanout Cap Trans Incr Path ------------------------------------------------------------------------------- clock ihdlc_RXCLK (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ohdlc_TXD_reg[2]/CK (DFFRHQXL) 0.00 0.00 1.00 r ohdlc_TXD_reg[2]/Q (DFFRHQXL) 0.97 0.91 1.91 r n691 (net) 2 0.04 0.00 1.91 r U573/Y (CLKBUFX20) 11.61 6.66 8.58 r ohdlc_TXD[2] (net) 1 33.55 0.00 8.58 r ohdlc_TXD[2] (out) 11.61 0.00 8.58 r data arrival time 8.58 clock ihdlc_RXCLK (rise edge) 50.00 50.00 clock network delay (ideal) 0.00 50.00 output external delay -5.00 45.00 data required time 45.00 ------------------------------------------------------------------------------- data required time 45.00 data arrival time -8.58 ------------------------------------------------------------------------------- slack (MET) 36.421⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -