📄 3c90x.h
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/*
3Com EtherLink 10/100 PCI (3C90x) Linux Network Driver, Copyright (c) 1999
3Com Corporation. All rights reserved.
3Com Linux Network Driver software is distributed as is, without any warranty
of any kind, either express or implied as further specified in the GNU Public
License. This software may be used and distributed according to the terms of
the GNU Public License, located in the file LICENSE.
3Com and EtherLink are registered trademarks of 3Com Corporation. Linux is a
registered trademarks of Linus Torvalds.
*/
//#define DEBUG 1
#define SERR_NEEDED 1
#include <linux/config.h>
#ifdef MODULE
#ifdef MODVERSIONS
#include <linux/modversions.h>
#endif
/* don't define kernel_verion in module.h */
#define __NO_VERSION__
#include <linux/module.h>
#include <linux/version.h>
#else
#define MOD_INC_USE_COUNT
#define MOD_DEC_USE_COUNT
#endif
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/ptrace.h>
#include <linux/errno.h>
#include <linux/in.h>
#include <linux/ioport.h>
#include <linux/malloc.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/timer.h>
#include <asm/irq.h>
#include <asm/bitops.h>
#include <asm/io.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/tqueue.h>
#ifndef LINUX_VERSION_CODE
#include <linux/version.h>
#endif
#if LINUX_VERSION_CODE <= 0x20200
#include <linux/bios32.h>
#endif
#if LINUX_VERSION_CODE < 0x10300
#define RUN_AT(x) (x)
#define DEV_ALLOC_SKB(length) alloc_skb(length, GFP_ATOMIC)
//#if defined(__alpha)
//#error "The Alpha architecture is only supported with kernel version 2.0."
//#endif
#define virt_to_bus(address) ((ULONG)address)
#define bus_to_virt(address) ((PVOID)address)
#define NR_IRQS 16
#else
#define RUN_AT(x) (jiffies + (x))
#define DEV_ALLOC_SKB(length) dev_alloc_skb(length)
#endif
#if LINUX_VERSION_CODE < 0x20159
#define DEV_FREE_SKB(skb) dev_kfree_skb(skb, FREE_WRITE);
#else
#define DEV_FREE_SKB(skb) dev_kfree_skb(skb);
#endif
#ifdef SA_SHIRQ
#define FREE_IRQ(irqnum, dev) free_irq(irqnum, dev)
#define REQUEST_IRQ(i,h,f,n,instance) request_irq(i,h,f,n,instance)
#define IRQ(irq, dev_id, pt_regs) (irq, dev_id, pt_regs)
#else
#define FREE_IRQ(irqnum, dev) free_irq(irqnum)
#define REQUEST_IRQ(i,h,f,n,instance) request_irq(i,h,f,n)
#define IRQ(irq, dev_id, pt_regs) (irq, pt_regs)
#endif
#if (LINUX_VERSION_CODE >= 0x10344)
#define NEW_MULTICAST
#include <linux/delay.h>
#else
#define udelay(microsec) \
do { int _i = 4*microsec; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0)
#endif
#if LINUX_VERSION_CODE >= 0x20200
#include <asm/spinlock.h>
#endif
#if LINUX_VERSION_CODE < 0x20138
#define test_and_set_bit(value, address) \
set_bit(value, address)
#endif
#define BIT_0 (1 << 0)
#define BIT_1 (1 << 1)
#define BIT_2 (1 << 2)
#define BIT_3 (1 << 3)
#define BIT_4 (1 << 4)
#define BIT_5 (1 << 5)
#define BIT_6 (1 << 6)
#define BIT_7 (1 << 7)
#define BIT_8 (1 << 8)
#define BIT_9 (1 << 9)
#define BIT_10 (1 << 10)
#define BIT_11 (1 << 11)
#define BIT_12 (1 << 12)
#define BIT_13 (1 << 13)
#define BIT_14 (1 << 14)
#define BIT_15 (1 << 15)
#define BIT_16 (1 << 16)
#define BIT_17 (1 << 17)
#define BIT_18 (1 << 18)
#define BIT_19 (1 << 19)
#define BIT_20 (1 << 20)
#define BIT_21 (1 << 21)
#define BIT_22 (1 << 22)
#define BIT_23 (1 << 23)
#define BIT_24 (1 << 24)
#define BIT_25 (1 << 25)
#define BIT_26 (1 << 26)
#define BIT_27 (1 << 27)
#define BIT_28 (1 << 28)
#define BIT_29 (1 << 29)
#define BIT_30 (1 << 30)
#define BIT_31 (1 << 31)
#ifndef HIBYTE
#define HIBYTE(_w) (((USHORT)(_w)) >> 8)
#endif
#ifndef LOBYTE
#define LOBYTE(_w) ((UCHAR)((_w) & 0xFF))
#endif
typedef char *PCHAR;
typedef long LONG;
typedef unsigned long ULONG;
typedef unsigned short USHORT;
typedef unsigned char UCHAR;
typedef void VOID;
typedef char CHAR;
typedef int INT;
typedef unsigned long *PULONG;
typedef unsigned short *PUSHORT;
typedef unsigned char *PUCHAR;
typedef void *PVOID;
typedef UCHAR BOOLEAN;
typedef BOOLEAN *PBOOLEAN;
typedef struct enet_statistics ENET_STATISTICS;
typedef struct dev_mc_list DEV_MC_LIST, *PDEV_MC_LIST;
typedef struct timer_list TIMER;
typedef struct tq_struct TASKQ;
#define FALSE 0
#define TRUE 1
//
// Linux Error code.
//
typedef ULONG LINUX_ERROR_CODE;
#define LINUX_ERROR_CODE_OUT_OF_RESOURCES 0x1
#define IN
#define OUT
/*
* Typedefs for Linux structures
*/
typedef struct device *PDEVICE;
typedef struct device DEVICE;
typedef struct ifreq *PIFREQ;
typedef struct sk_buff *PSKB;
typedef struct pt_regs *PTREGS;
typedef struct enet_statistics *PENET_STATISTICS;
/*
* 3Com Node Address
*/
#define EEPROM_NODE_ADDRESS_WORD_0 0x00
#define EEPROM_NODE_ADDRESS_WORD_1 0x01
#define EEPROM_NODE_ADDRESS_WORD_2 0x02
#define EEPROM_DEVICE_ID 0x03
/*++
Possible values:
0x9055 - PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX connector.
0x9056 - PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4 connector.
0x9004 - PCI 10BASE-T (TPO)
0x9005 - PCI 10BASE-T/10BASE-2/AUI(COMBO)
0x9006 - PCI 10BASE-T/10BASE-2/(TPC)
--*/
#define EEPROM_MANUFACTURING_DATE 0x04
typedef struct _MANUFACTURING_DATE {
USHORT Day:5;
USHORT Month:4;
USHORT Year:7;
} MANUFACTURING_DATE;
#define EEPROM_MANUFACTURING_DIVISION 0x05
#define EEPROM_MANUFACTURING_PRODUCT_CODE 0x06
#define EEPROM_MANUFACTURING_ID 0x07
#define EEPROM_PCI_PARAMETERS_1 0x08
typedef struct _PCI_PARAMETERS_1 {
USHORT Bit0:1;
USHORT Lower1Meg:1;
USHORT DisableMemoryBase:1;
USHORT D3SupportCold:1;
USHORT D1Support:1;
USHORT D2Support:1;
USHORT MinimumGrant:4;
USHORT MaximumLatency:6;
} PCI_PARAMETERS_1, *PPCI_PARAMETERS_1;
#define EEPROM_ROM_INFORMATION 0x09
typedef struct _ROM_INFORMATION {
USHORT Reserved:11;
USHORT ROMPresent:1;
//
// 0x00 - 64k * 8.
// 0x01 - 128k * 8.
// 0x1x - Reserved.
//
USHORT RomSize:2;
} ROM_INFORMATION, *PROM_INFORMATION;
/*
* OEM Node address
*/
#define EEPROM_OEM_NODE_ADDRESS_WORD_0 0x0A
#define EEPROM_OEM_NODE_ADDRESS_WORD_1 0x0B
#define EEPROM_OEM_NODE_ADDRESS_WORD_2 0x0C
#define EEPROM_SOFTWARE_INFORMATION_1 0x0D
typedef struct _SOFTWARE_INFORMATION_1 {
USHORT Reserved1:4;
#define EEPROM_OPTIMIZE_NORMAL 0x1
#define EEPROM_OPTIMIZE_FOR_THROUGHPUT 0x2
#define EEPROM_OPTIMIZE_FOR_CPU 0x3
USHORT OptimizeFor:2;
USHORT Reserved2:8;
USHORT LinkBeatDisable:1;
#define EEPROM_DISABLE_FULL_DUPLEX 0x00
#define EEPROM_ENABLE_FULL_DUPLEX 0x01
USHORT FullDuplexMode:1;
} SOFTWARE_INFORMATION_1, *PSOFTWARE_INFORMATION_1;
#define EEPROM_COMPATABILITY_WORD 0x0E
#define EEPROM_COMPATABILITY_LEVEL 0x00
typedef struct _COMPATABILITY_WORD {
USHORT WarningLevel:8;
USHORT FailureLevel:8;
} COMPATABILITY_WORD, *PCOMPATABILITY_WORD;
#define EEPROM_SOFTWARE_INFORMATION_2 0x0F
#define ENABLE_MWI_WORK 0x0020
typedef struct _SOFTWARE_INFORMATION_2 {
USHORT Reserved1:1;
USHORT BroadcastRxErrDone:1;
USHORT EncoderDecoderLoopBackErrDone:1;
USHORT WOLConnectorPresent:1;
USHORT PMEPulsed:1;
USHORT MWIErrDone:1;
USHORT AutoResetToD0:1;
USHORT D3Work:1;
} SOFTWARE_INFORMATION_2, *PSOFTWARE_INFORMATION_2;
#define EEPROM_CAPABILITIES_WORD 0x10
typedef struct _CAPABILITIES_WORD {
USHORT SupportsPlugNPlay:1;
USHORT SupportsFullDuplex:1;
USHORT SupportsLargePackets:1;
USHORT SupportsSlaveDMA:1;
USHORT SupportsSecondDMA:1;
USHORT SupportsFullBusMaster:1;
USHORT SupportsFragBusMaster:1;
USHORT SupportsCRCPassThrough:1;
USHORT SupportsTxDone:1;
USHORT SupportsNoTxLength:1;
USHORT SupportsRxRepeat:1;
USHORT Supports100Mbps:1;
USHORT SupportsPowerManagement:1;
} CAPABILITIES_WORD, *PCAPABILITIES_WORD;
#define EEPROM_RESERVED_LOCATION 0x11
#define EEPROM_INTERNAL_CONFIG_WORD_0 0x12
#define EEPROM_INTERNAL_CONFIG_WORD_1 0x13
#define EEPROM_ANALOG_DIAGNOSTICS 0x14
#define EEPROM_SOFTWARE_INFORMATION_3 0x15
typedef struct _SOFTWARE_INFORMATION_3 {
#define EEPROM_GENERIC_MII 0x00
#define EEPROM_100BASE_T4_MII 0x01
#define EEPROM_10BASE_T_MII 0x02
#define EEPROM_100BASE_TX_MII 0x03
#define EEPROM_10_BASE_T_AUTONEGOTIATION 0x04
#define EEPROM_100_BASE_TX_AUTONEGOTIATION 0x04
USHORT ForceXcvr:4;
USHORT Reserved:12;
} SOFTWARE_INFORMATION_3, *PSOFTWARE_INFORMATION_3;
/*
* Locations 0x1E - 0x1F are reserved.
*/
#define EEPROM_CHECKSUM_1 0x20
/*
* Locations 0x21 - 0x2F are reserved.
*/
#define EEPROM_SOS_PINS_1_TO_4 0x21
#define EEPROM_SOS_PINS_5_TO_7 0x22
/*
* Locations 0x00 - 0xFD are flexible format locations (4kb EEPROMs)
*/
#define EEPROM_CHECKSUM_2_UPPER 0xFE
#define EEPROM_CHECKSUM_2_LOWER 0xFF
/*
* Locations 0x00 - 0x3FD are flexible format locations (16Kb EEPROMs)
*/
#define EEPROM_CHECKSUM_3_UPPER 0x3FE
#define EEPROM_CHECKSUM_3_LOWER 0x3FF
#define EEPROM_COMMAND_MASK 0xE000
#define EEPROM_COMMAND_AUTOINIT_DONE 0xE000
#define EEPROM_COMMAND_PCI_CONFIG_WRITE 0xA000
#define EEPROM_COMMAND_REGISTER_WRITE 0x6000
#define EEPROM_COMMAND_TX_FIFO_WRITE 0x2000
#define EEPROM_CURRENT_WINDOW_MASK 0x7000
#define EEPROM_ADDRESS_MASK 0x00FF
#define EEPROM_TX_BYTE_COUNT 0x03FF
#define EEPROM_FLEXIBLE_FORMAT_START 0x40
#define EEPROM_WORD_ACCESS 0x1000
#define MAX_FLEX_EEPROM_SIZE 2048
#define EEPROM_WINDOW_0 (0x0 << 0x8)
#define EEPROM_WINDOW_1 (0x1 << 0x8)
#define EEPROM_WINDOW_2 (0x2 << 0x8)
#define EEPROM_WINDOW_3 (0x3 << 0x8)
#define EEPROM_WINDOW_4 (0x4 << 0x8)
#define EEPROM_WINDOW_5 (0x5 << 0x8)
#define EEPROM_WINDOW_6 (0x6 << 0x8)
#define EEPROM_WINDOW_7 (0x7 << 0x8)
typedef struct _PCI_CONFIG_CONFIGURATION_REGISTERS {
USHORT VendorId;
USHORT DeviceId;
USHORT Command;
USHORT Status;
UCHAR RevisionId;
UCHAR ClassCode[3];
UCHAR CacheLineSize;
UCHAR LatencyTimer;
UCHAR HeaderType;
UCHAR Reserved1;
ULONG IoBaseAddress;
ULONG MemoryBaseAddress;
ULONG Reserved2;
ULONG Reserved3;
ULONG Reserved4;
ULONG Reserved5;
ULONG Reserved6;
USHORT SubSystemVendorId;
USHORT SubSystemId;
ULONG BIOSRomControl;
UCHAR CapabilityPointer;
UCHAR Reserved7[3];
ULONG Reserved8;
UCHAR InterruptLine;
UCHAR InterruptPin;
UCHAR MinimumGrant;
UCHAR MaximumLatency;
ULONG Reserved9;
ULONG Reserved10;
ULONG Reserved11;
ULONG Reserved12;
UCHAR MediaTestModeLow;
UCHAR Reserved13[3];
UCHAR MediaTestModeHigh;
UCHAR Reserved14[3];
UCHAR MediaTestOutput;
UCHAR Reserved15[3];
UCHAR MediaTestPattern;
UCHAR Reserved16[3];
ULONG Reserved17[31];
UCHAR CapabilityId;
UCHAR NextPointer;
USHORT PowerManagementCapability;
USHORT PowerManagementControl;
UCHAR Reserved18;
UCHAR Data;
} PCI_CONFIG_CONFIGURATION_REGISTERS, *PPCI_CONFIG__CONFIGURATION_REGISTERS;
typedef struct _PCI_CONFIG_COMMAND {
USHORT IoSpace:1;
USHORT MemorySpace:1;
USHORT BusMasterEnable:1;
USHORT Reserved1:1;
USHORT MWIEnable:1;
USHORT Reserved2:1;
USHORT ParityErrorResponse:1;
USHORT Reserved3:1;
USHORT SERREnable:1;
} PCI_CONFIG_COMMAND, *PPCI_CONFIG_COMMAND;
typedef struct _PCI_CONFIG_STATUS {
USHORT Reserved1:4;
USHORT CapabilitiesList:1;
USHORT Reserved2:2;
USHORT FastBackToBack:1;
USHORT DmaParityDetected:1;
USHORT DevselTiming:2;
USHORT SignalTargetAbort:1;
USHORT ReceivedTargetAbort:1;
USHORT ReceivedMasterAbort:1;
USHORT SignaledSystemError:1;
USHORT DetectedParityError:1;
} PCI_CONFIG__STATUS, *PPCI_CONFIG_STATUS;
typedef struct _PCI_CONFIG_REVISION_ID {
UCHAR Revision:5;
UCHAR ChipVersion:3;
} PCI_CONFIG_REVISION_ID, *PCI_CONFIG_PREVISION_ID;
#define PCI_POWER_CONTROL 0xE0
#define PCI_PME_ENABLE 0x0100
#define PCI_PME_STATUS 0x8000
typedef struct _PCI_CONFIG_POWER_MANAGEMENT_CONTROL {
#define PCI_POWER_STATE_D0 0x00
#define PCI_POWER_STATE_D1 0x01
#define PCI_POWER_STATE_D2 0x02
#define PCI_POWER_STATE_D3 0x03
USHORT PowerState:2;
USHORT Reserved1:6;
USHORT PMEEnable:1;
USHORT DataSelect:4;
USHORT DataScale:2;
USHORT PMEStatus:1;
} PCI_CONFIG_POWER_MANAGEMENT_CONTROL,
*PPCI_CONFIG_POWER_MANAGEMENT_CONTROL;
//
// Supported PCI device id's
//
#define NIC_VENDOR_ID 0x10B7
#define NIC_PCI_DEVICE_ID_9055 0x9055
#define NIC_PCI_DEVICE_ID_9056 0x9056
#define NIC_PCI_DEVICE_ID_9058 0x9058
#define NIC_PCI_DEVICE_ID_9004 0x9004
#define NIC_PCI_DEVICE_ID_9005 0x9005
#define NIC_PCI_DEVICE_ID_9006 0x9006
#define NIC_PCI_DEVICE_ID_900A 0x900A
#define NIC_PCI_DEVICE_ID_905A 0x905A
#define NIC_PCI_DEVICE_ID_9200 0x9200
#define NIC_PCI_DEVICE_ID_9800 0x9800
#define NIC_PCI_DEVICE_ID_9805 0x9805
#define NIC_PCI_DEVICE_ID_4500 0x4500
#define NIC_PCI_DEVICE_ID_7646 0x7646
//
// ASIC versions.
//
#define NIC_ASIC_CYCLONE_KRAKATOA_LUCENT 0x0
#define NIC_ASIC_HURRICANE_TORNADO_LUCENT 0x1
#define NIC_ASIC_HURRICANE_NATIONAL 0x2
#define NIC_ASIC_HURRICANE_TORNADO_BROADCOM 0x3
//
// Window definitions.
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