util.asm

CY7C63743 usb键盘的源码

;========================================================================
;   FILE: util.asm 
;
;   contains utility functions that have no other place to live
;   
;   REVISION HISTORY
;
;   3/26/99 fixed get_keyboard_type to test usb condition for 50 msec
;   3/20/00 fixed get_keyboard_type to work properly with a USB 1.1 
;           compliant Host. 
;
;
;========================================================================


;========================================================================
; FUNCTION: get_keyboard_type
;
; Determines keyboard type 
;
;
; Returns:
;
;
;========================================================================


get_keyboard_type:

    mov     A,PS2_ENABLED_INTERRUPTS        ;enable ps2 (1 mS) interrupts        
    iowr    GLOBAL_INTERRUPT_REG
    mov     A,CLKH_DATAH
    iowr    USB_STATUS_CONTROL_REG          ;initialize control reg    
  
    ei


    mov     A,[dual_ifc_1ms]                   ;wait 10 ms
    add     A,50
.wait:
    iowr    WATCHDOG_REG
   cmp     A,[dual_ifc_1ms]
    jnz     .wait


    mov     A,[dual_ifc_1ms]                  ;set up to count 2 ms
    add     A,2 
	push    A 

  
	XPAGEOFF
.loop:
    pop		A																					
    cmp     A,[dual_ifc_1ms]                   ;7 check for counter = 0
    jz      .testusb                           ;5 it is, go try for USB
	push	A

;test for 4 consecutive samples of clock and data high,
;approximately every 2 us
   
.l1:
	iord	USB_STATUS_CONTROL_REG              ;5 read clock and data
	and	    A,(PS2_CLOCK_BIT + PS2_DATA_BIT)    ;4 mask off important bits
    jz     .loop                                ;5 loop if  zero

    nop
    nop
    nop

	iord	USB_STATUS_CONTROL_REG              ;5 read clock and data
	and	    A,(PS2_CLOCK_BIT + PS2_DATA_BIT)    ;4 mask off important bits
    jz     .loop                                ;5 loop if  zero
    nop
    nop
    nop

	iord	USB_STATUS_CONTROL_REG              ;5 read clock and data
	and	    A,(PS2_CLOCK_BIT + PS2_DATA_BIT)    ;4 mask off important bits
    jz     .loop                                ;5 loop if  zero
    nop
    nop
    nop

	iord	USB_STATUS_CONTROL_REG              ;5 read clock and data
	and	    A,(PS2_CLOCK_BIT + PS2_DATA_BIT)    ;4 mask off important bits
    jz     .loop                                ;5 loop if  zero

XPAGEON
    ;if we get here, we are ps2.
.ps2:
    mov     A,0ffh                          ;drive connect bit high
    iowr    PORT3_DATA_REG
    mov      A,PS2_KEYBOARD
    jmp     .exit

.testusb:
    mov     A,~P3_USB_CONN_MASK             ;drive connect bit low

    iowr    PORT3_DATA_REG

    DELAY   250
    DELAY   250

.usbforever:
	    
    iowr    WATCHDOG_REG
    iord	USB_STATUS_CONTROL_REG              ;while the host is forcing
	and	    A,(PS2_CLOCK_BIT + PS2_DATA_BIT)    ;SEO condition the program 
    jz     .usbforever                          ;is waiting 
                              					;
	cmp     A,DM                                ;check for D- high only

	jnz		.ps2								;D- is low (D+ is high),
												;the interface is not USB, has
 												;to be PS2


	mov     A,0ffh                          ;The interface looks USB, let's
											;do a further test to be sure
											;drive connect bit high
    iowr    PORT3_DATA_REG					;disconnect pull up resistor
											;on D-

	DELAY 	100


	iord	USB_STATUS_CONTROL_REG              ;test for D+ an D- low again
	and	    A,(PS2_CLOCK_BIT + PS2_DATA_BIT)    ; 
    jnz     .ps2                          		;D+ and D- not low (it is PS2) 


   .usb:                                        ;it's usb!
	mov     A,~P3_USB_CONN_MASK             	;drive connect bit low
	iowr    PORT3_DATA_REG						;enable pull up resistor on D-

    mov     A,0                                 ;     
    iowr    USB_STATUS_CONTROL_REG              ;initialize control reg 
    mov     A,USB_KEYBOARD
.exit:
    push    A
    di
    mov     A,0                                 ;disable interrupts      
    iowr    GLOBAL_INTERRUPT_REG
    pop     A
    ret